lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctly

Indent the AtomicOpsCap and AtomicOpsCtl fields to make it clear that these
are part of the DevCap2 and DevCtl2 registers.

The difference in the "lspci -vv" output looks like this:

        DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
-       AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+                AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
-       AtomicOpsCtl: ReqEn- EgressBlck-
+                AtomicOpsCtl: ReqEn- EgressBlck-

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/ls-caps.c b/ls-caps.c
index 30f371f062058ee729f6a1fbaa6da65d93069f03..1230746964e8f41da4d4730624f625384523277c 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1000,7 +1000,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
     {
-       printf("\t\tAtomicOpsCap:");
+       printf("\t\t\t AtomicOpsCap:");
        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
            type == PCI_EXP_TYPE_DOWNSTREAM)
          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
@@ -1026,7 +1026,7 @@ static void cap_express_dev2(struct device *d, int where, int type)
       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
     {
-      printf("\t\tAtomicOpsCtl:");
+      printf("\t\t\t AtomicOpsCtl:");
       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));

diff --git a/tests/cap-exp-dev2 b/tests/cap-exp-dev2
new file mode 100644 (file)
index 0000000..9b3bc9a
--- /dev/null
+++ b/tests/cap-exp-dev2
@@ -0,0 +1,327 @@
+00:1c.0 PCI bridge: Intel Corporation Device 9d10 (rev f1) (prog-if 00 [Normal decode])
+       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+       Latency: 0
+       Interrupt: pin A routed to IRQ 255
+       Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
+       I/O behind bridge: None
+       Memory behind bridge: f1100000-f11fffff [size=1M]
+       Prefetchable memory behind bridge: None
+       Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+       BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
+               PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+       Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+               DevCap: MaxPayload 256 bytes, PhantFunc 0
+                       ExtTag- RBE+
+               DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+                       RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+                       MaxPayload 256 bytes, MaxReadReq 128 bytes
+               DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+               LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
+                       ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
+               LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+                       ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+               LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+               SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+                       Slot #0, PowerLimit 10.000W; Interlock- NoCompl+
+               SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+                       Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+               SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+                       Changed: MRL- PresDet- LinkState+
+               RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
+               RootCap: CRSVisible-
+               RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+               DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
+                        AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+               DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
+                        AtomicOpsCtl: ReqEn- EgressBlck-
+               LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+                        Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+                        Compliance De-emphasis: -6dB
+               LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+                        EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+       Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit-
+               Address: 00000000  Data: 0000
+       Capabilities: [90] Subsystem: Lenovo Device 2238
+       Capabilities: [a0] Power Management version 3
+               Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+               Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+       Capabilities: [100 v1] Advanced Error Reporting
+               UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+               UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+               UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+               CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+               CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+               AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+                       MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+               HeaderLog: 00000000 00000000 00000000 00000000
+               RootCmd: CERptEn- NFERptEn- FERptEn-
+               RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
+                        FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
+               ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
+       Capabilities: [140 v1] Access Control Services
+               ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
+               ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+       Capabilities: [200 v1] L1 PM Substates
+               L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+                         PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
+               L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
+                          T_CommonMode=60us LTR1.2_Threshold=163840ns
+               L1SubCtl2: T_PwrOn=60us
+       Capabilities: [220 v1] #19
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