From: David Woodhouse Date: Thu, 15 Oct 2015 18:44:16 +0000 (+0100) Subject: Decode PASID and PRI extended capabilities X-Git-Tag: v3.4.1~5 X-Git-Url: http://git.ipfire.org/?p=thirdparty%2Fpciutils.git;a=commitdiff_plain;h=a858df0dd24afcc66630e6bc7c06d72c1a98dbbe Decode PASID and PRI extended capabilities --- diff --git a/lib/header.h b/lib/header.h index 8ee7565..f7cdee7 100644 --- a/lib/header.h +++ b/lib/header.h @@ -224,8 +224,10 @@ #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */ #define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */ #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ +#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ #define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */ #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ +#define PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID */ #define PCI_EXT_CAP_ID_L1PM 0x1e /* L1 PM Substates */ /*** Definitions of capabilities ***/ @@ -1042,6 +1044,17 @@ #define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ #define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */ +/* Page Request Interface */ +#define PCI_PRI_CTRL 0x04 /* PRI Control Register */ +#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ +#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ +#define PCI_PRI_STATUS 0x06 /* PRI status register */ +#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ +#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ +#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ +#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ +#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ + /* Transaction Processing Hints */ #define PCI_TPH_CAPABILITIES 4 #define PCI_TPH_INTVEC_SUP (1<<1) /* Supports interrupt vector mode */ @@ -1060,6 +1073,15 @@ #define PCI_LTR_SCALE_MASK (7) #define PCI_LTR_MAX_NOSNOOP 6 /* 16 bit value */ +/* Process Address Space ID */ +#define PCI_PASID_CAP 0x04 /* PASID feature register */ +#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ +#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ +#define PCI_PASID_CAP_WIDTH(x) (((x) >> 8) & 0x1f) /* Max PASID Width */ +#define PCI_PASID_CTRL 0x06 /* PASID control register */ +#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ +#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ +#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index c6f217e..ab9fd7a 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -204,6 +204,54 @@ cap_ats(struct device *d, int where) FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); } +static void +cap_pri(struct device *d, int where) +{ + u16 w; + u32 l; + + printf("Page Request Interface (PRI)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) + return; + + w = get_conf_word(d, where + PCI_PRI_CTRL); + printf("\t\tPRICtl: Enable%c, Reset%c\n", + FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); + w = get_conf_word(d, where + PCI_PRI_STATUS); + printf("\t\tPRISta: RF%c, UPRGI%c, Stopped%c\n", + FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), + FLAG(w, PCI_PRI_STATUS_STOPPED)); + l = get_conf_long(d, where + PCI_PRI_MAX_REQ); + printf("\t\tPage Request Capacity: %08x, ", l); + l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); + printf("Page Request Allocation: %08x\n", l); +} + +static void +cap_pasid(struct device *d, int where) +{ + u16 w; + + printf("Process Address Space ID (PASID)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PASID_CAP, 4)) + return; + + w = get_conf_word(d, where + PCI_PASID_CAP); + printf("\t\tPASIDCap: Exec%c, Priv%c, Max PASID Width: %02x\n", + FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), + PCI_PASID_CAP_WIDTH(w)); + w = get_conf_word(d, where + PCI_PASID_CTRL); + printf("\t\tPASIDCtl: Enable%c, Exec%c, Priv%c\n", + FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), + FLAG(w, PCI_PASID_CTRL_PRIV)); +} + static void cap_sriov(struct device *d, int where) { @@ -572,12 +620,18 @@ show_ext_caps(struct device *d) case PCI_EXT_CAP_ID_SRIOV: cap_sriov(d, where); break; + case PCI_EXT_CAP_ID_PRI: + cap_pri(d, where); + break; case PCI_EXT_CAP_ID_TPH: cap_tph(d, where); break; case PCI_EXT_CAP_ID_LTR: cap_ltr(d, where); break; + case PCI_EXT_CAP_ID_PASID: + cap_pasid(d, where); + break; case PCI_EXT_CAP_ID_L1PM: cap_l1pm(d, where); break; diff --git a/tests/cap-pasid-pri b/tests/cap-pasid-pri new file mode 100644 index 0000000..dfebbf3 --- /dev/null +++ b/tests/cap-pasid-pri @@ -0,0 +1,293 @@ +00:02.0 VGA compatible controller: Intel Corporation Sky Lake Integrated Graphics (rev 07) (prog-if 00 [VGA controller]) + Subsystem: Intel Corporation Sky Lake Integrated Graphics + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [40] Vendor Specific Information: Len=0c + Capabilities: [70] Express (v2) Root Complex Integrated Endpoint, MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- + DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled + Capabilities: [ac] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee00018 Data: 0000 + Capabilities: [d0] Power Management version 2 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Process Address Space ID (PASID) + PASIDCap: Exec+, Priv-, Max PASID Width: 14 + PASIDCtl: Enable+, Exec+, Priv- + Capabilities: [200 v1] Address Translation Service (ATS) + ATSCap: Invalidate Queue Depth: 00 + ATSCtl: Enable+, Smallest Translation Unit: 00 + Capabilities: [300 v1] Page Request Interface (PRI) + PRICtl: Enable-, Reset- + PRISta: RF-, UPRGI-, Stopped- + Page Request Capacity: 00008000, Page Request Allocation: 00000000 + Kernel driver in use: i915 +00: 86 80 1e 19 07 04 10 00 07 00 00 03 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