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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
71e8a915 | 21 | |
b6a0aa05 | 22 | #include "qemu/osdep.h" |
0d09e41a | 23 | #include "hw/i386/pc.h" |
fff123b8 | 24 | #include "hw/southbridge/piix.h" |
64552b6b | 25 | #include "hw/irq.h" |
0d09e41a PB |
26 | #include "hw/isa/apm.h" |
27 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 28 | #include "hw/pci/pci.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
0d09e41a | 30 | #include "hw/acpi/acpi.h" |
54d31236 | 31 | #include "sysemu/runstate.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
da34e65c | 33 | #include "qapi/error.h" |
1de7afc9 | 34 | #include "qemu/range.h" |
022c62cb | 35 | #include "exec/address-spaces.h" |
9e047b98 | 36 | #include "hw/acpi/pcihp.h" |
81cea5e7 | 37 | #include "hw/acpi/cpu_hotplug.h" |
5e1b5d93 | 38 | #include "hw/acpi/cpu.h" |
c24d5e0b | 39 | #include "hw/hotplug.h" |
34774320 IM |
40 | #include "hw/mem/pc-dimm.h" |
41 | #include "hw/acpi/memory_hotplug.h" | |
43f50410 | 42 | #include "hw/acpi/acpi_dev_interface.h" |
91ab2ed7 | 43 | #include "hw/xen/xen.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
2e5b09fd | 45 | #include "hw/core/cpu.h" |
b37d56ec | 46 | #include "trace.h" |
50d8ff8b | 47 | |
ac404095 | 48 | #define GPE_BASE 0xafe0 |
23910d3f | 49 | #define GPE_LEN 4 |
c177684c | 50 | |
ac404095 | 51 | struct pci_status { |
7faa8075 | 52 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
53 | uint32_t down; |
54 | }; | |
55 | ||
93d89f63 | 56 | typedef struct PIIX4PMState { |
6a6b5580 AF |
57 | /*< private >*/ |
58 | PCIDevice parent_obj; | |
59 | /*< public >*/ | |
56e5b2a1 | 60 | |
af11110b | 61 | MemoryRegion io; |
277e9340 MT |
62 | uint32_t io_base; |
63 | ||
b65b93f2 | 64 | MemoryRegion io_gpe; |
355bf2e5 | 65 | ACPIREGS ar; |
93d89f63 IY |
66 | |
67 | APMState apm; | |
68 | ||
93d89f63 | 69 | PMSMBus smb; |
e8ec0571 | 70 | uint32_t smb_io_base; |
93d89f63 IY |
71 | |
72 | qemu_irq irq; | |
93d89f63 | 73 | qemu_irq smi_irq; |
61e66c62 | 74 | int smm_enabled; |
6141dbfe | 75 | Notifier machine_ready; |
d010f91c | 76 | Notifier powerdown_notifier; |
ac404095 | 77 | |
9e047b98 MT |
78 | AcpiPciHpState acpi_pci_hotplug; |
79 | bool use_acpi_pci_hotplug; | |
80 | ||
459ae5ea GN |
81 | uint8_t disable_s3; |
82 | uint8_t disable_s4; | |
83 | uint8_t s4_val; | |
b8622725 | 84 | |
16bcab97 | 85 | bool cpu_hotplug_legacy; |
81cea5e7 | 86 | AcpiCpuHotplug gpe_cpu; |
5e1b5d93 | 87 | CPUHotplugState cpuhp_state; |
34774320 IM |
88 | |
89 | MemHotplugState acpi_memory_hotplug; | |
93d89f63 IY |
90 | } PIIX4PMState; |
91 | ||
74e445f6 PC |
92 | #define PIIX4_PM(obj) \ |
93 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
94 | ||
56e5b2a1 GH |
95 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
96 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 97 | |
93d89f63 IY |
98 | #define ACPI_ENABLE 0xf1 |
99 | #define ACPI_DISABLE 0xf0 | |
100 | ||
355bf2e5 | 101 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 102 | { |
355bf2e5 | 103 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
06313503 | 104 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
105 | } |
106 | ||
93d89f63 IY |
107 | static void apm_ctrl_changed(uint32_t val, void *arg) |
108 | { | |
109 | PIIX4PMState *s = arg; | |
6a6b5580 | 110 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
111 | |
112 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 113 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
afd6895b PB |
114 | if (val == ACPI_ENABLE || val == ACPI_DISABLE) { |
115 | return; | |
116 | } | |
93d89f63 | 117 | |
6a6b5580 | 118 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
119 | if (s->smi_irq) { |
120 | qemu_irq_raise(s->smi_irq); | |
121 | } | |
122 | } | |
123 | } | |
124 | ||
93d89f63 IY |
125 | static void pm_io_space_update(PIIX4PMState *s) |
126 | { | |
6a6b5580 | 127 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 | 128 | |
277e9340 MT |
129 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
130 | s->io_base &= 0xffc0; | |
93d89f63 | 131 | |
af11110b | 132 | memory_region_transaction_begin(); |
6a6b5580 | 133 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
277e9340 | 134 | memory_region_set_address(&s->io, s->io_base); |
af11110b | 135 | memory_region_transaction_commit(); |
93d89f63 IY |
136 | } |
137 | ||
24fe083d GH |
138 | static void smbus_io_space_update(PIIX4PMState *s) |
139 | { | |
6a6b5580 AF |
140 | PCIDevice *d = PCI_DEVICE(s); |
141 | ||
142 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
143 | s->smb_io_base &= 0xffc0; |
144 | ||
145 | memory_region_transaction_begin(); | |
6a6b5580 | 146 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
147 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
148 | memory_region_transaction_commit(); | |
93d89f63 IY |
149 | } |
150 | ||
151 | static void pm_write_config(PCIDevice *d, | |
152 | uint32_t address, uint32_t val, int len) | |
153 | { | |
154 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
155 | if (range_covers_byte(address, len, 0x80) || |
156 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 157 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
158 | } |
159 | if (range_covers_byte(address, len, 0xd2) || | |
160 | ranges_overlap(address, len, 0x90, 4)) { | |
161 | smbus_io_space_update((PIIX4PMState *)d); | |
162 | } | |
93d89f63 IY |
163 | } |
164 | ||
165 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
166 | { | |
167 | PIIX4PMState *s = opaque; | |
168 | ||
169 | pm_io_space_update(s); | |
2b4e573c | 170 | smbus_io_space_update(s); |
93d89f63 IY |
171 | return 0; |
172 | } | |
173 | ||
23910d3f IY |
174 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
175 | { \ | |
176 | .name = (stringify(_field)), \ | |
177 | .version_id = 0, \ | |
23910d3f IY |
178 | .info = &vmstate_info_uint16, \ |
179 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 180 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
181 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
182 | } | |
183 | ||
4cf3e6f3 AW |
184 | static const VMStateDescription vmstate_gpe = { |
185 | .name = "gpe", | |
186 | .version_id = 1, | |
187 | .minimum_version_id = 1, | |
d49805ae | 188 | .fields = (VMStateField[]) { |
23910d3f IY |
189 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
190 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
191 | VMSTATE_END_OF_LIST() |
192 | } | |
193 | }; | |
194 | ||
195 | static const VMStateDescription vmstate_pci_status = { | |
196 | .name = "pci_status", | |
197 | .version_id = 1, | |
198 | .minimum_version_id = 1, | |
d49805ae | 199 | .fields = (VMStateField[]) { |
e358edc8 IM |
200 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
201 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), | |
4cf3e6f3 AW |
202 | VMSTATE_END_OF_LIST() |
203 | } | |
204 | }; | |
205 | ||
9e047b98 MT |
206 | static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) |
207 | { | |
208 | PIIX4PMState *s = opaque; | |
209 | return s->use_acpi_pci_hotplug; | |
210 | } | |
211 | ||
212 | static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) | |
213 | { | |
214 | PIIX4PMState *s = opaque; | |
215 | return !s->use_acpi_pci_hotplug; | |
216 | } | |
217 | ||
f816a62d IM |
218 | static bool vmstate_test_use_memhp(void *opaque) |
219 | { | |
220 | PIIX4PMState *s = opaque; | |
221 | return s->acpi_memory_hotplug.is_enabled; | |
222 | } | |
223 | ||
224 | static const VMStateDescription vmstate_memhp_state = { | |
225 | .name = "piix4_pm/memhp", | |
226 | .version_id = 1, | |
227 | .minimum_version_id = 1, | |
228 | .minimum_version_id_old = 1, | |
5cd8cada | 229 | .needed = vmstate_test_use_memhp, |
f816a62d IM |
230 | .fields = (VMStateField[]) { |
231 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), | |
232 | VMSTATE_END_OF_LIST() | |
233 | } | |
234 | }; | |
235 | ||
679dd1a9 IM |
236 | static bool vmstate_test_use_cpuhp(void *opaque) |
237 | { | |
238 | PIIX4PMState *s = opaque; | |
239 | return !s->cpu_hotplug_legacy; | |
240 | } | |
241 | ||
242 | static int vmstate_cpuhp_pre_load(void *opaque) | |
243 | { | |
244 | Object *obj = OBJECT(opaque); | |
245 | object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); | |
246 | return 0; | |
247 | } | |
248 | ||
249 | static const VMStateDescription vmstate_cpuhp_state = { | |
250 | .name = "piix4_pm/cpuhp", | |
251 | .version_id = 1, | |
252 | .minimum_version_id = 1, | |
253 | .minimum_version_id_old = 1, | |
254 | .needed = vmstate_test_use_cpuhp, | |
255 | .pre_load = vmstate_cpuhp_pre_load, | |
256 | .fields = (VMStateField[]) { | |
257 | VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), | |
258 | VMSTATE_END_OF_LIST() | |
259 | } | |
260 | }; | |
261 | ||
4ab2f2a8 CM |
262 | static bool piix4_vmstate_need_smbus(void *opaque, int version_id) |
263 | { | |
264 | return pm_smbus_vmstate_needed(); | |
265 | } | |
266 | ||
b0b873a0 MT |
267 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
268 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
269 | * and minimum_version_id to 2 below (which breaks migration from | |
270 | * qemu 1.2). | |
271 | * | |
272 | */ | |
93d89f63 IY |
273 | static const VMStateDescription vmstate_acpi = { |
274 | .name = "piix4_pm", | |
b0b873a0 MT |
275 | .version_id = 3, |
276 | .minimum_version_id = 3, | |
93d89f63 | 277 | .post_load = vmstate_acpi_post_load, |
d49805ae | 278 | .fields = (VMStateField[]) { |
6a6b5580 | 279 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
280 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
281 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
282 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 283 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
4ab2f2a8 CM |
284 | VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, |
285 | pmsmb_vmstate, PMSMBus), | |
e720677e | 286 | VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), |
355bf2e5 GH |
287 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
288 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
e358edc8 IM |
289 | VMSTATE_STRUCT_TEST( |
290 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], | |
291 | PIIX4PMState, | |
292 | vmstate_test_no_use_acpi_pci_hotplug, | |
293 | 2, vmstate_pci_status, | |
294 | struct AcpiPciHpPciStatus), | |
9e047b98 MT |
295 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
296 | vmstate_test_use_acpi_pci_hotplug), | |
93d89f63 | 297 | VMSTATE_END_OF_LIST() |
f816a62d | 298 | }, |
5cd8cada JQ |
299 | .subsections = (const VMStateDescription*[]) { |
300 | &vmstate_memhp_state, | |
679dd1a9 | 301 | &vmstate_cpuhp_state, |
5cd8cada | 302 | NULL |
93d89f63 IY |
303 | } |
304 | }; | |
305 | ||
217e8ef9 | 306 | static void piix4_pm_reset(DeviceState *dev) |
93d89f63 | 307 | { |
217e8ef9 | 308 | PIIX4PMState *s = PIIX4_PM(dev); |
6a6b5580 AF |
309 | PCIDevice *d = PCI_DEVICE(s); |
310 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
311 | |
312 | pci_conf[0x58] = 0; | |
313 | pci_conf[0x59] = 0; | |
314 | pci_conf[0x5a] = 0; | |
315 | pci_conf[0x5b] = 0; | |
316 | ||
4d09d37c GN |
317 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
318 | pci_conf[0x80] = 0; | |
319 | ||
61e66c62 | 320 | if (!s->smm_enabled) { |
93d89f63 IY |
321 | /* Mark SMM as already inited (until KVM supports SMM). */ |
322 | pci_conf[0x5B] = 0x02; | |
323 | } | |
c046e8c4 | 324 | pm_io_space_update(s); |
e358edc8 | 325 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
93d89f63 IY |
326 | } |
327 | ||
d010f91c | 328 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 329 | { |
d010f91c | 330 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 331 | |
355bf2e5 GH |
332 | assert(s != NULL); |
333 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
334 | } |
335 | ||
ec266f40 DH |
336 | static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
337 | DeviceState *dev, Error **errp) | |
338 | { | |
9040e6df WY |
339 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
340 | ||
ec266f40 DH |
341 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
342 | acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); | |
9040e6df WY |
343 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
344 | if (!s->acpi_memory_hotplug.is_enabled) { | |
345 | error_setg(errp, | |
346 | "memory hotplug is not enabled: %s.memory-hotplug-support " | |
347 | "is not set", object_get_typename(OBJECT(s))); | |
348 | } | |
349 | } else if ( | |
ec266f40 DH |
350 | !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
351 | error_setg(errp, "acpi: device pre plug request for not supported" | |
352 | " device type: %s", object_get_typename(OBJECT(dev))); | |
353 | } | |
354 | } | |
355 | ||
f1adc360 IM |
356 | static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, |
357 | DeviceState *dev, Error **errp) | |
9e047b98 | 358 | { |
c24d5e0b | 359 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
f1adc360 | 360 | |
9040e6df | 361 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
75f27498 XG |
362 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
363 | nvdimm_acpi_plug_cb(hotplug_dev, dev); | |
364 | } else { | |
365 | acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, | |
366 | dev, errp); | |
367 | } | |
34774320 | 368 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
2bed1ba7 | 369 | acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); |
5e1b5d93 IM |
370 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
371 | if (s->cpu_hotplug_legacy) { | |
372 | legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); | |
373 | } else { | |
374 | acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
375 | } | |
f1adc360 | 376 | } else { |
ec266f40 | 377 | g_assert_not_reached(); |
f1adc360 | 378 | } |
c24d5e0b | 379 | } |
9e047b98 | 380 | |
14d5a28f IM |
381 | static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
382 | DeviceState *dev, Error **errp) | |
c24d5e0b IM |
383 | { |
384 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); | |
f1adc360 | 385 | |
64fec58e TC |
386 | if (s->acpi_memory_hotplug.is_enabled && |
387 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
0058c082 | 388 | acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, |
64fec58e TC |
389 | dev, errp); |
390 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { | |
c97adf3c DH |
391 | acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, |
392 | dev, errp); | |
8872c25a IM |
393 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
394 | !s->cpu_hotplug_legacy) { | |
395 | acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
f1adc360 IM |
396 | } else { |
397 | error_setg(errp, "acpi: device unplug request for not supported device" | |
398 | " type: %s", object_get_typename(OBJECT(dev))); | |
399 | } | |
9e047b98 MT |
400 | } |
401 | ||
c0e57a60 TC |
402 | static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, |
403 | DeviceState *dev, Error **errp) | |
404 | { | |
f7d3e29d TC |
405 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
406 | ||
407 | if (s->acpi_memory_hotplug.is_enabled && | |
408 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
409 | acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); | |
c97adf3c DH |
410 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
411 | acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, | |
412 | errp); | |
8872c25a IM |
413 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
414 | !s->cpu_hotplug_legacy) { | |
415 | acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); | |
f7d3e29d TC |
416 | } else { |
417 | error_setg(errp, "acpi: device unplug for not supported device" | |
418 | " type: %s", object_get_typename(OBJECT(dev))); | |
419 | } | |
c0e57a60 TC |
420 | } |
421 | ||
9e8dd451 | 422 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
423 | { |
424 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
425 | PCIDevice *d = PCI_DEVICE(s); |
426 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
427 | uint8_t *pci_conf; |
428 | ||
6a6b5580 | 429 | pci_conf = d->config; |
b6f32962 | 430 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 431 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 432 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
433 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
434 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
6141dbfe PB |
435 | } |
436 | ||
277e9340 MT |
437 | static void piix4_pm_add_propeties(PIIX4PMState *s) |
438 | { | |
439 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; | |
440 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; | |
441 | static const uint32_t gpe0_blk = GPE_BASE; | |
442 | static const uint32_t gpe0_blk_len = GPE_LEN; | |
443 | static const uint16_t sci_int = 9; | |
444 | ||
445 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
446 | &acpi_enable_cmd, NULL); | |
447 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
448 | &acpi_disable_cmd, NULL); | |
449 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, | |
450 | &gpe0_blk, NULL); | |
451 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, | |
452 | &gpe0_blk_len, NULL); | |
453 | object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, | |
454 | &sci_int, NULL); | |
455 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, | |
456 | &s->io_base, NULL); | |
457 | } | |
458 | ||
9af21dbe | 459 | static void piix4_pm_realize(PCIDevice *dev, Error **errp) |
93d89f63 | 460 | { |
74e445f6 | 461 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
462 | uint8_t *pci_conf; |
463 | ||
6a6b5580 | 464 | pci_conf = dev->config; |
93d89f63 IY |
465 | pci_conf[0x06] = 0x80; |
466 | pci_conf[0x07] = 0x02; | |
93d89f63 | 467 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
468 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
469 | ||
93d89f63 | 470 | /* APM */ |
42d8a3cf | 471 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 472 | |
61e66c62 | 473 | if (!s->smm_enabled) { |
93d89f63 IY |
474 | /* Mark SMM as already inited to prevent SMM from running. KVM does not |
475 | * support SMM mode. */ | |
476 | pci_conf[0x5B] = 0x02; | |
477 | } | |
478 | ||
479 | /* XXX: which specification is used ? The i82731AB has different | |
480 | mappings */ | |
e8ec0571 IY |
481 | pci_conf[0x90] = s->smb_io_base | 1; |
482 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 483 | pci_conf[0xd2] = 0x09; |
45726b6e | 484 | pm_smbus_init(DEVICE(dev), &s->smb, true); |
24fe083d | 485 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
486 | memory_region_add_subregion(pci_address_space_io(dev), |
487 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 488 | |
64bde0f3 | 489 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 490 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
491 | memory_region_add_subregion(pci_address_space_io(dev), |
492 | 0, &s->io); | |
93d89f63 | 493 | |
77d58b1e | 494 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 495 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 496 | acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); |
355bf2e5 | 497 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 498 | |
d010f91c IM |
499 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
500 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 501 | |
6141dbfe PB |
502 | s->machine_ready.notify = piix4_pm_machine_ready; |
503 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
56e5b2a1 | 504 | |
fd56e061 DG |
505 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), |
506 | pci_get_bus(dev), s); | |
94d1cc5f | 507 | qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort); |
e8ec0571 | 508 | |
277e9340 | 509 | piix4_pm_add_propeties(s); |
e8ec0571 IY |
510 | } |
511 | ||
a5c82852 AF |
512 | I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
513 | qemu_irq sci_irq, qemu_irq smi_irq, | |
61e66c62 | 514 | int smm_enabled, DeviceState **piix4_pm) |
e8ec0571 | 515 | { |
74e445f6 | 516 | DeviceState *dev; |
e8ec0571 IY |
517 | PIIX4PMState *s; |
518 | ||
74e445f6 PC |
519 | dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
520 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); | |
781bbd6b IM |
521 | if (piix4_pm) { |
522 | *piix4_pm = dev; | |
523 | } | |
93d89f63 | 524 | |
74e445f6 | 525 | s = PIIX4_PM(dev); |
93d89f63 | 526 | s->irq = sci_irq; |
93d89f63 | 527 | s->smi_irq = smi_irq; |
61e66c62 | 528 | s->smm_enabled = smm_enabled; |
91ab2ed7 IM |
529 | if (xen_enabled()) { |
530 | s->use_acpi_pci_hotplug = false; | |
531 | } | |
e8ec0571 | 532 | |
74e445f6 | 533 | qdev_init_nofail(dev); |
93d89f63 IY |
534 | |
535 | return s->smb.smbus; | |
536 | } | |
537 | ||
b65b93f2 | 538 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 539 | { |
633aa0ac | 540 | PIIX4PMState *s = opaque; |
355bf2e5 | 541 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 542 | |
b37d56ec | 543 | trace_piix4_gpe_readb(addr, width, val); |
93d89f63 IY |
544 | return val; |
545 | } | |
546 | ||
b65b93f2 GH |
547 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
548 | unsigned width) | |
93d89f63 | 549 | { |
633aa0ac | 550 | PIIX4PMState *s = opaque; |
633aa0ac | 551 | |
b37d56ec | 552 | trace_piix4_gpe_writeb(addr, width, val); |
355bf2e5 | 553 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
06313503 | 554 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
555 | } |
556 | ||
b65b93f2 GH |
557 | static const MemoryRegionOps piix4_gpe_ops = { |
558 | .read = gpe_readb, | |
559 | .write = gpe_writeb, | |
560 | .valid.min_access_size = 1, | |
561 | .valid.max_access_size = 4, | |
562 | .impl.min_access_size = 1, | |
563 | .impl.max_access_size = 1, | |
564 | .endianness = DEVICE_LITTLE_ENDIAN, | |
565 | }; | |
566 | ||
16bcab97 IM |
567 | |
568 | static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) | |
569 | { | |
570 | PIIX4PMState *s = PIIX4_PM(obj); | |
571 | ||
572 | return s->cpu_hotplug_legacy; | |
573 | } | |
574 | ||
575 | static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) | |
576 | { | |
577 | PIIX4PMState *s = PIIX4_PM(obj); | |
578 | ||
679dd1a9 IM |
579 | assert(!value); |
580 | if (s->cpu_hotplug_legacy && value == false) { | |
581 | acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, | |
582 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
583 | } | |
16bcab97 IM |
584 | s->cpu_hotplug_legacy = value; |
585 | } | |
586 | ||
56e5b2a1 GH |
587 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
588 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 589 | { |
64bde0f3 PB |
590 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
591 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 592 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 593 | |
78c2d872 | 594 | acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, |
e358edc8 | 595 | s->use_acpi_pci_hotplug); |
b8622725 | 596 | |
16bcab97 IM |
597 | s->cpu_hotplug_legacy = true; |
598 | object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", | |
599 | piix4_get_cpu_hotplug_legacy, | |
600 | piix4_set_cpu_hotplug_legacy, | |
601 | NULL); | |
96e3e12b IM |
602 | legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, |
603 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
34774320 IM |
604 | |
605 | if (s->acpi_memory_hotplug.is_enabled) { | |
80db0e78 IM |
606 | acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, |
607 | ACPI_MEMORY_HOTPLUG_BASE); | |
34774320 | 608 | } |
93d89f63 | 609 | } |
5fdae20c | 610 | |
43f50410 IM |
611 | static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
612 | { | |
613 | PIIX4PMState *s = PIIX4_PM(adev); | |
614 | ||
615 | acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); | |
76623d00 IM |
616 | if (!s->cpu_hotplug_legacy) { |
617 | acpi_cpu_ospm_status(&s->cpuhp_state, list); | |
618 | } | |
43f50410 IM |
619 | } |
620 | ||
eaf23bf7 IM |
621 | static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
622 | { | |
623 | PIIX4PMState *s = PIIX4_PM(adev); | |
624 | ||
625 | acpi_send_gpe_event(&s->ar, s->irq, ev); | |
626 | } | |
627 | ||
5fdae20c IM |
628 | static Property piix4_pm_properties[] = { |
629 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
630 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), | |
631 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), | |
632 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), | |
633 | DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, | |
634 | use_acpi_pci_hotplug, true), | |
34774320 IM |
635 | DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, |
636 | acpi_memory_hotplug.is_enabled, true), | |
5fdae20c IM |
637 | DEFINE_PROP_END_OF_LIST(), |
638 | }; | |
639 | ||
640 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
641 | { | |
642 | DeviceClass *dc = DEVICE_CLASS(klass); | |
643 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
c24d5e0b | 644 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
43f50410 | 645 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
5fdae20c | 646 | |
9af21dbe | 647 | k->realize = piix4_pm_realize; |
5fdae20c IM |
648 | k->config_write = pm_write_config; |
649 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
650 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
651 | k->revision = 0x03; | |
652 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
217e8ef9 | 653 | dc->reset = piix4_pm_reset; |
5fdae20c IM |
654 | dc->desc = "PM"; |
655 | dc->vmsd = &vmstate_acpi; | |
656 | dc->props = piix4_pm_properties; | |
657 | /* | |
658 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
659 | * e.g. by mips_malta_init() | |
660 | */ | |
e90f2a8c | 661 | dc->user_creatable = false; |
2897ae02 | 662 | dc->hotpluggable = false; |
ec266f40 | 663 | hc->pre_plug = piix4_device_pre_plug_cb; |
f1adc360 | 664 | hc->plug = piix4_device_plug_cb; |
14d5a28f | 665 | hc->unplug_request = piix4_device_unplug_request_cb; |
c0e57a60 | 666 | hc->unplug = piix4_device_unplug_cb; |
43f50410 | 667 | adevc->ospm_status = piix4_ospm_status; |
eaf23bf7 | 668 | adevc->send_event = piix4_send_gpe; |
ac35f13b | 669 | adevc->madt_cpu = pc_madt_cpu_entry; |
5fdae20c IM |
670 | } |
671 | ||
672 | static const TypeInfo piix4_pm_info = { | |
673 | .name = TYPE_PIIX4_PM, | |
674 | .parent = TYPE_PCI_DEVICE, | |
675 | .instance_size = sizeof(PIIX4PMState), | |
676 | .class_init = piix4_pm_class_init, | |
c24d5e0b IM |
677 | .interfaces = (InterfaceInfo[]) { |
678 | { TYPE_HOTPLUG_HANDLER }, | |
43f50410 | 679 | { TYPE_ACPI_DEVICE_IF }, |
fd3b02c8 | 680 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
c24d5e0b IM |
681 | { } |
682 | } | |
5fdae20c IM |
683 | }; |
684 | ||
685 | static void piix4_pm_register_types(void) | |
686 | { | |
687 | type_register_static(&piix4_pm_info); | |
688 | } | |
689 | ||
690 | type_init(piix4_pm_register_types) |