[thirdparty/u-boot.git] / Bindings / phy / qcom,sc8280xp-qmp-pcie-phy.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (PCIe, SC8280XP)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  The QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    enum:
      - qcom,sa8775p-qmp-gen4x2-pcie-phy
      - qcom,sa8775p-qmp-gen4x4-pcie-phy
      - qcom,sc8180x-qmp-pcie-phy
      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
      - qcom,sdm845-qhp-pcie-phy
      - qcom,sdm845-qmp-pcie-phy
      - qcom,sdx55-qmp-pcie-phy
      - qcom,sdx65-qmp-gen4x2-pcie-phy
      - qcom,sm8150-qmp-gen3x1-pcie-phy
      - qcom,sm8150-qmp-gen3x2-pcie-phy
      - qcom,sm8250-qmp-gen3x1-pcie-phy
      - qcom,sm8250-qmp-gen3x2-pcie-phy
      - qcom,sm8250-qmp-modem-pcie-phy
      - qcom,sm8350-qmp-gen3x1-pcie-phy
      - qcom,sm8450-qmp-gen3x1-pcie-phy
      - qcom,sm8450-qmp-gen4x2-pcie-phy
      - qcom,sm8550-qmp-gen3x2-pcie-phy
      - qcom,sm8550-qmp-gen4x2-pcie-phy
      - qcom,sm8650-qmp-gen3x2-pcie-phy
      - qcom,sm8650-qmp-gen4x2-pcie-phy

  reg:
    minItems: 1
    maxItems: 2

  clocks:
    minItems: 5
    maxItems: 7

  clock-names:
    minItems: 5
    items:
      - const: aux
      - const: cfg_ahb
      - const: ref
      - enum: [rchng, refgen]
      - const: pipe
      - const: pipediv2
      - const: phy_aux

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    items:
      - const: phy
      - const: phy_nocsr

  vdda-phy-supply: true

  vdda-pll-supply: true

  vdda-qref-supply: true

  qcom,4ln-config-sel:
    description: PCIe 4-lane configuration
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle of TCSR syscon
          - description: offset of PCIe 4-lane configuration register
          - description: offset of configuration bit for this PHY

  "#clock-cells":
    const: 0

  clock-output-names:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply
  - "#clock-cells"
  - clock-output-names
  - "#phy-cells"

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
    then:
      properties:
        reg:
          items:
            - description: port a
            - description: port b
      required:
        - qcom,4ln-config-sel
    else:
      properties:
        reg:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8180x-qmp-pcie-phy
              - qcom,sdm845-qhp-pcie-phy
              - qcom,sdm845-qmp-pcie-phy
              - qcom,sdx55-qmp-pcie-phy
              - qcom,sm8150-qmp-gen3x1-pcie-phy
              - qcom,sm8150-qmp-gen3x2-pcie-phy
              - qcom,sm8250-qmp-gen3x1-pcie-phy
              - qcom,sm8250-qmp-gen3x2-pcie-phy
              - qcom,sm8250-qmp-modem-pcie-phy
              - qcom,sm8350-qmp-gen3x1-pcie-phy
              - qcom,sm8450-qmp-gen3x1-pcie-phy
              - qcom,sm8450-qmp-gen3x2-pcie-phy
              - qcom,sm8550-qmp-gen3x2-pcie-phy
              - qcom,sm8550-qmp-gen4x2-pcie-phy
              - qcom,sm8650-qmp-gen3x2-pcie-phy
              - qcom,sm8650-qmp-gen4x2-pcie-phy
    then:
      properties:
        clocks:
          maxItems: 5
        clock-names:
          maxItems: 5

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-qmp-gen3x1-pcie-phy
              - qcom,sc8280xp-qmp-gen3x2-pcie-phy
              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
    then:
      properties:
        clocks:
          minItems: 6
        clock-names:
          minItems: 6

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sa8775p-qmp-gen4x2-pcie-phy
              - qcom,sa8775p-qmp-gen4x4-pcie-phy
    then:
      properties:
        clocks:
          minItems: 7
        clock-names:
          minItems: 7

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8550-qmp-gen4x2-pcie-phy
              - qcom,sm8650-qmp-gen4x2-pcie-phy
    then:
      properties:
        resets:
          minItems: 2
        reset-names:
          minItems: 2
    else:
      properties:
        resets:
          maxItems: 1
        reset-names:
          maxItems: 1

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

    pcie2b_phy: phy@1c18000 {
      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
      reg = <0x01c18000 0x2000>;

      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
               <&gcc GCC_PCIE_2B_PIPE_CLK>,
               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
      clock-names = "aux", "cfg_ahb", "ref", "rchng",
                    "pipe", "pipediv2";

      power-domains = <&gcc PCIE_2B_GDSC>;

      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
      reset-names = "phy";

      vdda-phy-supply = <&vreg_l6d>;
      vdda-pll-supply = <&vreg_l4d>;

      #clock-cells = <0>;
      clock-output-names = "pcie_2b_pipe_clk";

      #phy-cells = <0>;
    };

    pcie2a_phy: phy@1c24000 {
      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;

      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
               <&gcc GCC_PCIE_2A_PIPE_CLK>,
               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
      clock-names = "aux", "cfg_ahb", "ref", "rchng",
                    "pipe", "pipediv2";

      power-domains = <&gcc PCIE_2A_GDSC>;

      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
      reset-names = "phy";

      vdda-phy-supply = <&vreg_l6d>;
      vdda-pll-supply = <&vreg_l4d>;

      qcom,4ln-config-sel = <&tcsr 0xa044 0>;

      #clock-cells = <0>;
      clock-output-names = "pcie_2a_pipe_clk";

      #phy-cells = <0>;
    };
Commit	Line	Data
53633a89 TR	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
	8
	9	maintainers:
	10	- Vinod Koul <vkoul@kernel.org>
	11
	12	description:
	13	The QMP PHY controller supports physical layer functionality for a number of
	14	controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
	15
	16	properties:
	17	compatible:
	18	enum:
	19	- qcom,sa8775p-qmp-gen4x2-pcie-phy
	20	- qcom,sa8775p-qmp-gen4x4-pcie-phy
	21	- qcom,sc8180x-qmp-pcie-phy
	22	- qcom,sc8280xp-qmp-gen3x1-pcie-phy
	23	- qcom,sc8280xp-qmp-gen3x2-pcie-phy
	24	- qcom,sc8280xp-qmp-gen3x4-pcie-phy
	25	- qcom,sdm845-qhp-pcie-phy
	26	- qcom,sdm845-qmp-pcie-phy
	27	- qcom,sdx55-qmp-pcie-phy
	28	- qcom,sdx65-qmp-gen4x2-pcie-phy
	29	- qcom,sm8150-qmp-gen3x1-pcie-phy
	30	- qcom,sm8150-qmp-gen3x2-pcie-phy
	31	- qcom,sm8250-qmp-gen3x1-pcie-phy
	32	- qcom,sm8250-qmp-gen3x2-pcie-phy
	33	- qcom,sm8250-qmp-modem-pcie-phy
	34	- qcom,sm8350-qmp-gen3x1-pcie-phy
	35	- qcom,sm8450-qmp-gen3x1-pcie-phy
	36	- qcom,sm8450-qmp-gen4x2-pcie-phy
	37	- qcom,sm8550-qmp-gen3x2-pcie-phy
	38	- qcom,sm8550-qmp-gen4x2-pcie-phy
93743d24 TR	39	- qcom,sm8650-qmp-gen3x2-pcie-phy
93743d24 TR	40	- qcom,sm8650-qmp-gen4x2-pcie-phy
53633a89 TR	41
	42	reg:
	43	minItems: 1
	44	maxItems: 2
	45
	46	clocks:
	47	minItems: 5
	48	maxItems: 7
	49
	50	clock-names:
	51	minItems: 5
	52	items:
	53	- const: aux
	54	- const: cfg_ahb
	55	- const: ref
	56	- enum: [rchng, refgen]
	57	- const: pipe
	58	- const: pipediv2
	59	- const: phy_aux
	60
	61	power-domains:
	62	maxItems: 1
	63
	64	resets:
	65	minItems: 1
	66	maxItems: 2
	67
	68	reset-names:
	69	minItems: 1
	70	items:
	71	- const: phy
	72	- const: phy_nocsr
	73
	74	vdda-phy-supply: true
	75
	76	vdda-pll-supply: true
	77
	78	vdda-qref-supply: true
	79
	80	qcom,4ln-config-sel:
	81	description: PCIe 4-lane configuration
	82	$ref: /schemas/types.yaml#/definitions/phandle-array
	83	items:
	84	- items:
	85	- description: phandle of TCSR syscon
	86	- description: offset of PCIe 4-lane configuration register
	87	- description: offset of configuration bit for this PHY
	88
	89	"#clock-cells":
	90	const: 0
	91
	92	clock-output-names:
	93	maxItems: 1
	94
	95	"#phy-cells":
	96	const: 0
	97
	98	required:
	99	- compatible
	100	- reg
	101	- clocks
	102	- clock-names
	103	- resets
	104	- reset-names
105	- vdda-phy-supply
106	- vdda-pll-supply
107	- "#clock-cells"
108	- clock-output-names
109	- "#phy-cells"
110
111	additionalProperties: false
112
113	allOf:
114	- if:
115	properties:
116	compatible:
117	contains:
118	enum:
119	- qcom,sc8280xp-qmp-gen3x4-pcie-phy
120	then:
121	properties:
122	reg:
123	items:
124	- description: port a
125	- description: port b
126	required:
127	- qcom,4ln-config-sel
128	else:
129	properties:
130	reg:
131	maxItems: 1
132
133	- if:
134	properties:
135	compatible:
136	contains:
137	enum:
138	- qcom,sc8180x-qmp-pcie-phy
139	- qcom,sdm845-qhp-pcie-phy
140	- qcom,sdm845-qmp-pcie-phy
141	- qcom,sdx55-qmp-pcie-phy
142	- qcom,sm8150-qmp-gen3x1-pcie-phy
143	- qcom,sm8150-qmp-gen3x2-pcie-phy
144	- qcom,sm8250-qmp-gen3x1-pcie-phy
145	- qcom,sm8250-qmp-gen3x2-pcie-phy
146	- qcom,sm8250-qmp-modem-pcie-phy
147	- qcom,sm8350-qmp-gen3x1-pcie-phy
148	- qcom,sm8450-qmp-gen3x1-pcie-phy
149	- qcom,sm8450-qmp-gen3x2-pcie-phy
150	- qcom,sm8550-qmp-gen3x2-pcie-phy
151	- qcom,sm8550-qmp-gen4x2-pcie-phy
93743d24 TR	152	- qcom,sm8650-qmp-gen3x2-pcie-phy
93743d24 TR	153	- qcom,sm8650-qmp-gen4x2-pcie-phy
53633a89 TR	154	then:
	155	properties:
	156	clocks:
	157	maxItems: 5
	158	clock-names:
	159	maxItems: 5
	160
	161	- if:
	162	properties:
	163	compatible:
	164	contains:
	165	enum:
	166	- qcom,sc8280xp-qmp-gen3x1-pcie-phy
	167	- qcom,sc8280xp-qmp-gen3x2-pcie-phy
	168	- qcom,sc8280xp-qmp-gen3x4-pcie-phy
	169	then:
	170	properties:
	171	clocks:
	172	minItems: 6
	173	clock-names:
	174	minItems: 6
	175
	176	- if:
	177	properties:
	178	compatible:
	179	contains:
	180	enum:
	181	- qcom,sa8775p-qmp-gen4x2-pcie-phy
	182	- qcom,sa8775p-qmp-gen4x4-pcie-phy
	183	then:
	184	properties:
	185	clocks:
	186	minItems: 7
	187	clock-names:
	188	minItems: 7
	189
	190	- if:
	191	properties:
	192	compatible:
	193	contains:
	194	enum:
	195	- qcom,sm8550-qmp-gen4x2-pcie-phy
93743d24	196	- qcom,sm8650-qmp-gen4x2-pcie-phy
53633a89 TR	197	then:
	198	properties:
	199	resets:
	200	minItems: 2
	201	reset-names:
	202	minItems: 2
	203	else:
	204	properties:
	205	resets:
	206	maxItems: 1
	207	reset-names:
	208	maxItems: 1
	209
	210	examples:
	211	- \|
	212	#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
	213
	214	pcie2b_phy: phy@1c18000 {
	215	compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
	216	reg = <0x01c18000 0x2000>;
	217
	218	clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
	219	<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
	220	<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
	221	<&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
	222	<&gcc GCC_PCIE_2B_PIPE_CLK>,
	223	<&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
	224	clock-names = "aux", "cfg_ahb", "ref", "rchng",
	225	"pipe", "pipediv2";
	226
	227	power-domains = <&gcc PCIE_2B_GDSC>;
	228
	229	resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
	230	reset-names = "phy";
	231
	232	vdda-phy-supply = <&vreg_l6d>;
	233	vdda-pll-supply = <&vreg_l4d>;
	234
	235	#clock-cells = <0>;
	236	clock-output-names = "pcie_2b_pipe_clk";
	237
	238	#phy-cells = <0>;
	239	};
	240
	241	pcie2a_phy: phy@1c24000 {
	242	compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
	243	reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
	244
	245	clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
	246	<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
	247	<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
	248	<&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
	249	<&gcc GCC_PCIE_2A_PIPE_CLK>,
	250	<&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
	251	clock-names = "aux", "cfg_ahb", "ref", "rchng",
	252	"pipe", "pipediv2";
	253
	254	power-domains = <&gcc PCIE_2A_GDSC>;
	255
	256	resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
	257	reset-names = "phy";
	258
	259	vdda-phy-supply = <&vreg_l6d>;
	260	vdda-pll-supply = <&vreg_l4d>;
261
262	qcom,4ln-config-sel = <&tcsr 0xa044 0>;
263
264	#clock-cells = <0>;
265	clock-output-names = "pcie_2a_pipe_clk";
266
267	#phy-cells = <0>;
268	};