]>
Commit | Line | Data |
---|---|---|
ba1ed5b0 | 1 | config ARCH_MAP_SYSMEM |
11232139 | 2 | depends on SANDBOX |
ba1ed5b0 TR |
3 | def_bool y |
4 | ||
a350c6a6 MY |
5 | config CREATE_ARCH_SYMLINK |
6 | bool | |
7 | ||
9a387128 MY |
8 | config HAVE_ARCH_IOREMAP |
9 | bool | |
10 | ||
ab92b38a TR |
11 | config SYS_CACHE_SHIFT_4 |
12 | bool | |
13 | ||
14 | config SYS_CACHE_SHIFT_5 | |
15 | bool | |
16 | ||
17 | config SYS_CACHE_SHIFT_6 | |
18 | bool | |
19 | ||
20 | config SYS_CACHE_SHIFT_7 | |
21 | bool | |
22 | ||
24c4ac84 DC |
23 | config 32BIT |
24 | bool | |
25 | ||
26 | config 64BIT | |
27 | bool | |
28 | ||
ab92b38a TR |
29 | config SYS_CACHELINE_SIZE |
30 | int | |
31 | default 128 if SYS_CACHE_SHIFT_7 | |
32 | default 64 if SYS_CACHE_SHIFT_6 | |
33 | default 32 if SYS_CACHE_SHIFT_5 | |
34 | default 16 if SYS_CACHE_SHIFT_4 | |
35 | # Fall-back for MIPS | |
36 | default 32 if MIPS | |
37 | ||
0b2fa98a SG |
38 | config LINKER_LIST_ALIGN |
39 | int | |
40 | default 32 if SANDBOX | |
41 | default 8 if ARM64 || X86 | |
42 | default 4 | |
43 | help | |
44 | Force the each linker list to be aligned to this boundary. This | |
45 | is required if ll_entry_get() is used, since otherwise the linker | |
46 | may add padding into the table, thus breaking it. | |
47 | See linker_lists.rst for full details. | |
48 | ||
51631259 MY |
49 | choice |
50 | prompt "Architecture select" | |
51 | default SANDBOX | |
52 | ||
53 | config ARC | |
54 | bool "ARC architecture" | |
5ed063d1 | 55 | select ARC_TIMER |
3daa7c7b | 56 | select CLK |
7b56432c | 57 | select DM |
5ed063d1 MS |
58 | select HAVE_PRIVATE_LIBGCC |
59 | select SUPPORT_OF_CONTROL | |
ab92b38a | 60 | select SYS_CACHE_SHIFT_7 |
3daa7c7b | 61 | select TIMER |
83505a7e TR |
62 | select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN |
63 | select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN | |
51631259 MY |
64 | |
65 | config ARM | |
66 | bool "ARM architecture" | |
8f969651 | 67 | select ARCH_SUPPORTS_LTO |
a350c6a6 | 68 | select CREATE_ARCH_SYMLINK |
64b77ed2 | 69 | select HAVE_PRIVATE_LIBGCC if !ARM64 |
01537235 | 70 | select SUPPORT_ACPI |
783e6a72 | 71 | select SUPPORT_OF_CONTROL |
51631259 | 72 | |
51631259 MY |
73 | config M68K |
74 | bool "M68000 architecture" | |
6463fd8f | 75 | select HAVE_PRIVATE_LIBGCC |
1e48392e | 76 | select USE_PRIVATE_LIBGCC |
405fc830 DW |
77 | select SYS_BOOT_GET_CMDLINE |
78 | select SYS_BOOT_GET_KBD | |
ab92b38a | 79 | select SYS_CACHE_SHIFT_4 |
abe0f879 | 80 | select SUPPORT_OF_CONTROL |
51631259 MY |
81 | |
82 | config MICROBLAZE | |
83 | bool "MicroBlaze architecture" | |
783e6a72 | 84 | select SUPPORT_OF_CONTROL |
a36d8672 MS |
85 | imply CMD_TIMER |
86 | imply SPL_REGMAP if SPL | |
87 | imply SPL_TIMER if SPL | |
88 | imply TIMER | |
89 | imply XILINX_TIMER | |
51631259 MY |
90 | |
91 | config MIPS | |
92 | bool "MIPS architecture" | |
9a387128 | 93 | select HAVE_ARCH_IOREMAP |
45ccec8f | 94 | select HAVE_PRIVATE_LIBGCC |
0fc13a90 | 95 | select SUPPORT_OF_CONTROL |
1dd56db5 | 96 | select SPL_SEPARATE_BSS if SPL |
51631259 | 97 | |
51631259 MY |
98 | config NIOS2 |
99 | bool "Nios II architecture" | |
bcae80e9 | 100 | select CPU |
5ed063d1 | 101 | select DM |
448e2b63 | 102 | select DM_EVENT |
5ed063d1 MS |
103 | select OF_CONTROL |
104 | select SUPPORT_OF_CONTROL | |
08a00cba | 105 | imply CMD_DM |
51631259 | 106 | |
51631259 MY |
107 | config PPC |
108 | bool "PowerPC architecture" | |
45ccec8f | 109 | select HAVE_PRIVATE_LIBGCC |
c1c61573 | 110 | select SUPPORT_OF_CONTROL |
405fc830 DW |
111 | select SYS_BOOT_GET_CMDLINE |
112 | select SYS_BOOT_GET_KBD | |
51631259 | 113 | |
068feb9b | 114 | config RISCV |
117a433d | 115 | bool "RISC-V architecture" |
7c8d210b | 116 | select CREATE_ARCH_SYMLINK |
b17e280b | 117 | select SUPPORT_ACPI |
068feb9b | 118 | select SUPPORT_OF_CONTROL |
bf6cc82c BM |
119 | select OF_CONTROL |
120 | select DM | |
448e2b63 | 121 | select DM_EVENT |
57b9900c | 122 | imply SPL_SEPARATE_BSS if SPL |
cd1f45c2 | 123 | imply DM_SERIAL |
cd1f45c2 BM |
124 | imply DM_MMC |
125 | imply DM_SPI | |
126 | imply DM_SPI_FLASH | |
127 | imply BLK | |
128 | imply CLK | |
129 | imply MTD | |
130 | imply TIMER | |
bf6cc82c | 131 | imply CMD_DM |
8c59f202 LA |
132 | imply SPL_DM |
133 | imply SPL_OF_CONTROL | |
134 | imply SPL_LIBCOMMON_SUPPORT | |
135 | imply SPL_LIBGENERIC_SUPPORT | |
2a736066 | 136 | imply SPL_SERIAL |
8c59f202 | 137 | imply SPL_TIMER |
068feb9b | 138 | |
51631259 MY |
139 | config SANDBOX |
140 | bool "Sandbox" | |
94bb891e | 141 | select ARCH_SUPPORTS_LTO |
e5ec4815 | 142 | select BOARD_LATE_INIT |
efc06448 | 143 | select BZIP2 |
512369a7 | 144 | select CMD_POWEROFF if CMDLINE |
58d423b8 | 145 | select DM |
448e2b63 | 146 | select DM_EVENT |
0518e7a2 | 147 | select DM_FUZZING_ENGINE |
5ed063d1 MS |
148 | select DM_GPIO |
149 | select DM_I2C | |
558e1257 | 150 | select DM_KEYBOARD |
5ed063d1 | 151 | select DM_MMC |
58d423b8 | 152 | select DM_SERIAL |
58d423b8 | 153 | select DM_SPI |
5ed063d1 | 154 | select DM_SPI_FLASH |
efc06448 | 155 | select GZIP_COMPRESSED |
68e54040 | 156 | select IO_TRACE |
d56b4b19 | 157 | select LZO |
db04ff42 | 158 | select MTD |
1c0bc80a | 159 | select OF_BOARD_SETUP |
bb413337 | 160 | select PCI_ENDPOINT |
5ed063d1 MS |
161 | select SPI |
162 | select SUPPORT_OF_CONTROL | |
512369a7 | 163 | select SYSRESET_CMD_POWEROFF if CMD_POWEROFF |
ab92b38a | 164 | select SYS_CACHE_SHIFT_4 |
57c675d6 | 165 | select IRQ |
512369a7 | 166 | select SUPPORT_EXTENSION_SCAN if CMDLINE |
e1722fcb | 167 | select SUPPORT_ACPI |
0f1caa98 | 168 | imply BITREVERSE |
919e7a8f | 169 | select BLOBLIST |
1b457e75 | 170 | imply LTO |
08a00cba | 171 | imply CMD_DM |
6ca5ff3f | 172 | imply CMD_EXCEPTION |
ded48cdc | 173 | imply CMD_GETTIME |
551c3934 | 174 | imply CMD_HASH |
594e8d1c | 175 | imply CMD_IO |
7d0f5c13 | 176 | imply CMD_IOTRACE |
ee7c0e71 | 177 | imply CMD_LZMADEC |
a4298dda | 178 | imply CMD_SF |
5ed063d1 | 179 | imply CMD_SF_TEST |
91d27a17 TR |
180 | imply CRC32_VERIFY |
181 | imply FAT_WRITE | |
31b8217e | 182 | imply FIRMWARE |
0518e7a2 | 183 | imply FUZZING_ENGINE_SANDBOX |
221a949e | 184 | imply HASH_VERIFY |
91d27a17 | 185 | imply LZMA |
fe39e8e0 | 186 | imply TEE |
0a60a81b JW |
187 | imply AVB_VERIFY |
188 | imply LIBAVB | |
189 | imply CMD_AVB | |
d3adee1d | 190 | imply PARTITION_TYPE_GUID |
7c591a84 IO |
191 | imply SCP03 |
192 | imply CMD_SCP03 | |
0a60a81b | 193 | imply UDP_FUNCTION_FASTBOOT |
4f89d494 BM |
194 | imply VIRTIO_MMIO |
195 | imply VIRTIO_PCI | |
196 | imply VIRTIO_SANDBOX | |
197 | imply VIRTIO_BLK | |
198 | imply VIRTIO_NET | |
2a049572 | 199 | imply DM_SOUND |
bb413337 | 200 | imply PCI_SANDBOX_EP |
c882163b | 201 | imply PCH |
ec9594a5 AM |
202 | imply PHYLIB |
203 | imply DM_MDIO | |
c3d9f3f8 | 204 | imply DM_MDIO_MUX |
0992a90d | 205 | imply ACPI |
3b65ee34 SG |
206 | imply ACPI_PMC |
207 | imply ACPI_PMC_SANDBOX | |
208 | imply CMD_PMC | |
4a4830cf | 209 | imply CMD_CLONE |
f158ba15 | 210 | imply SILENT_CONSOLE |
51bb3384 | 211 | imply BOOTARGS_SUBST |
ff98da06 CM |
212 | imply PHY_FIXED |
213 | imply DM_DSA | |
95300f20 | 214 | imply CMD_EXTENSION |
93e1edff | 215 | imply KEYBOARD |
6405ab7a | 216 | imply PHYSMEM |
437992d3 | 217 | imply GENERATE_ACPI_TABLE |
059df562 | 218 | imply BINMAN |
04291ee0 AG |
219 | imply CMD_MBR |
220 | imply CMD_MMC | |
909b15ca SG |
221 | imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE |
222 | imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE | |
223 | imply CMD_SYSBOOT if BOOTSTD_FULL | |
51631259 MY |
224 | |
225 | config SH | |
226 | bool "SuperH architecture" | |
45ccec8f | 227 | select HAVE_PRIVATE_LIBGCC |
8c2c4635 | 228 | select SUPPORT_OF_CONTROL |
51631259 | 229 | |
51631259 MY |
230 | config X86 |
231 | bool "x86 architecture" | |
98987902 SG |
232 | select SUPPORT_SPL |
233 | select SUPPORT_TPL | |
a350c6a6 | 234 | select CREATE_ARCH_SYMLINK |
58d423b8 | 235 | select DM |
3bf9a8e8 | 236 | select HAVE_ARCH_IOMAP |
5ed063d1 MS |
237 | select HAVE_PRIVATE_LIBGCC |
238 | select OF_CONTROL | |
4f0faacb | 239 | select PCI |
e1722fcb | 240 | select SUPPORT_ACPI |
5ed063d1 | 241 | select SUPPORT_OF_CONTROL |
ab92b38a | 242 | select SYS_CACHE_SHIFT_6 |
0ce9c576 | 243 | select TIMER |
5ed063d1 | 244 | select USE_PRIVATE_LIBGCC |
0ce9c576 | 245 | select X86_TSC_TIMER |
543d091e | 246 | select IRQ |
bcd4e6f3 | 247 | imply HAS_ROM if X86_RESET_VECTOR |
24357dfd | 248 | imply BLK |
08a00cba | 249 | imply CMD_DM |
5ed063d1 MS |
250 | imply CMD_FPGA_LOADMK |
251 | imply CMD_GETTIME | |
252 | imply CMD_IO | |
253 | imply CMD_IRQ | |
254 | imply CMD_PCI | |
a4298dda | 255 | imply CMD_SF |
5ed063d1 MS |
256 | imply CMD_SF_TEST |
257 | imply CMD_ZBOOT | |
4f0faacb BM |
258 | imply DM_GPIO |
259 | imply DM_KEYBOARD | |
b7c6baef | 260 | imply DM_MMC |
4f0faacb | 261 | imply DM_RTC |
b630f8b3 | 262 | imply SCSI |
5ed063d1 | 263 | imply DM_SERIAL |
db04ff42 | 264 | imply MTD |
4f0faacb BM |
265 | imply DM_SPI |
266 | imply DM_SPI_FLASH | |
267 | imply DM_USB | |
91caa3bb | 268 | imply LAST_STAGE_INIT |
b86986c7 | 269 | imply VIDEO |
b37b7b20 | 270 | imply SYSRESET |
09259fce | 271 | imply SPL_SYSRESET |
b37b7b20 | 272 | imply SYSRESET_X86 |
f58ad98a CP |
273 | imply USB_ETHER_ASIX |
274 | imply USB_ETHER_SMSC95XX | |
5ed063d1 | 275 | imply USB_HOST_ETHER |
c882163b | 276 | imply PCH |
6405ab7a | 277 | imply PHYSMEM |
31d5261d | 278 | imply RTC_MC146818 |
0992a90d | 279 | imply ACPI |
27ba6289 | 280 | imply ACPIGEN if !QEMU && !EFI_APP |
839d66cd SG |
281 | imply SYSINFO if GENERATE_SMBIOS_TABLE |
282 | imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE | |
d6b318de | 283 | imply TIMESTAMP |
51631259 | 284 | |
98987902 SG |
285 | # Thing to enable for when SPL/TPL are enabled: SPL |
286 | imply SPL_DM | |
287 | imply SPL_OF_LIBFDT | |
9ca00684 | 288 | imply SPL_DRIVERS_MISC |
83061dbd | 289 | imply SPL_GPIO |
e556d3d6 | 290 | imply SPL_PINCTRL |
98987902 SG |
291 | imply SPL_LIBCOMMON_SUPPORT |
292 | imply SPL_LIBGENERIC_SUPPORT | |
2a736066 | 293 | imply SPL_SERIAL |
98987902 | 294 | imply SPL_SPI_FLASH_SUPPORT |
ea2ca7e1 | 295 | imply SPL_SPI |
98987902 SG |
296 | imply SPL_OF_CONTROL |
297 | imply SPL_TIMER | |
298 | imply SPL_REGMAP | |
299 | imply SPL_SYSCON | |
300 | # TPL | |
301 | imply TPL_DM | |
9ca00684 | 302 | imply TPL_DRIVERS_MISC |
83061dbd | 303 | imply TPL_GPIO |
e556d3d6 | 304 | imply TPL_PINCTRL |
98987902 SG |
305 | imply TPL_LIBCOMMON_SUPPORT |
306 | imply TPL_LIBGENERIC_SUPPORT | |
2a736066 | 307 | imply TPL_SERIAL |
98987902 SG |
308 | imply TPL_OF_CONTROL |
309 | imply TPL_TIMER | |
310 | imply TPL_REGMAP | |
311 | imply TPL_SYSCON | |
312 | ||
c978b524 CZ |
313 | config XTENSA |
314 | bool "Xtensa architecture" | |
315 | select CREATE_ARCH_SYMLINK | |
316 | select SUPPORT_OF_CONTROL | |
317 | ||
51631259 MY |
318 | endchoice |
319 | ||
3174e4e8 MY |
320 | config SYS_ARCH |
321 | string | |
322 | help | |
323 | This option should contain the architecture name to build the | |
324 | appropriate arch/<CONFIG_SYS_ARCH> directory. | |
325 | All the architectures should specify this option correctly. | |
326 | ||
327 | config SYS_CPU | |
328 | string | |
329 | help | |
330 | This option should contain the CPU name to build the correct | |
331 | arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory. | |
332 | ||
333 | This is optional. For those targets without the CPU directory, | |
334 | leave this option empty. | |
335 | ||
336 | config SYS_SOC | |
337 | string | |
338 | help | |
339 | This option should contain the SoC name to build the directory | |
340 | arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>. | |
341 | ||
342 | This is optional. For those targets without the SoC directory, | |
343 | leave this option empty. | |
344 | ||
345 | config SYS_VENDOR | |
346 | string | |
347 | help | |
348 | This option should contain the vendor name of the target board. | |
349 | If it is set and | |
350 | board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common | |
351 | directory is compiled. | |
352 | If CONFIG_SYS_BOARD is also set, the sources under | |
353 | board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled. | |
354 | ||
355 | This is optional. For those targets without the vendor directory, | |
356 | leave this option empty. | |
357 | ||
358 | config SYS_BOARD | |
359 | string | |
360 | help | |
361 | This option should contain the name of the target board. | |
362 | If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> | |
363 | or board/<CONFIG_SYS_BOARD> directory is compiled depending on | |
364 | whether CONFIG_SYS_VENDOR is set or not. | |
365 | ||
366 | This is optional. For those targets without the board directory, | |
367 | leave this option empty. | |
368 | ||
369 | config SYS_CONFIG_NAME | |
3dd14868 TR |
370 | string "Board header file" if ARCH_MESON || ARCH_VERSAL || \ |
371 | ARCH_VERSAL_NET || ARCH_ZYNQ || ARCH_ZYNQMP || \ | |
372 | ARCH_ZYNQMP_R5 || MICROBLAZE || NIOS2 | |
373 | default "meson64" if ARCH_MESON | |
374 | default "microblaze-generic" if MICROBLAZE | |
375 | default "xilinx_versal" if ARCH_VERSAL | |
376 | default "xilinx_versal_net" if ARCH_VERSAL_NET | |
377 | default "xilinx_zynqmp" if ARCH_ZYNQMP | |
378 | default "xilinx_zynqmp_r5" if ARCH_ZYNQMP_R5 | |
379 | default "zynq-common" if ARCH_ZYNQ | |
3174e4e8 MY |
380 | help |
381 | This option should contain the base name of board header file. | |
382 | The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h | |
383 | should be included from include/config.h. | |
384 | ||
add49671 VR |
385 | config SYS_DISABLE_DCACHE_OPS |
386 | bool | |
387 | help | |
388 | This option disables dcache flush and dcache invalidation | |
389 | operations. For example, on coherent systems where cache | |
390 | operatios are not required, enable this option to avoid them. | |
391 | Note that, its up to the individual architectures to implement | |
392 | this functionality. | |
393 | ||
be7dbb60 | 394 | config SYS_IMMR |
dd2986ac | 395 | hex "Address for the Internal Memory-Mapped Registers (IMMR) window" |
be7dbb60 TR |
396 | depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A |
397 | default 0xFF000000 if MPC8xx | |
398 | default 0xF0000000 if ARCH_MPC8313 | |
399 | default 0xE0000000 if MPC83xx && !ARCH_MPC8313 | |
400 | default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 | |
39f42fe2 T |
401 | default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ |
402 | ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ | |
403 | ARCH_P2020 | |
be7dbb60 TR |
404 | default SYS_CCSRBAR_DEFAULT |
405 | help | |
406 | Address for the Internal Memory-Mapped Registers (IMMR) window used | |
407 | to configure the features of many Freescale / NXP SoCs. | |
408 | ||
e52fca22 TR |
409 | config MONITOR_IS_IN_RAM |
410 | bool "U-Boot is loaded in to RAM by a pre-loader" | |
411 | depends on M68K || NIOS2 | |
412 | ||
c394e8d0 | 413 | menu "Skipping low level initialization functions" |
11232139 | 414 | depends on ARM || MIPS || RISCV |
c394e8d0 HS |
415 | |
416 | config SKIP_LOWLEVEL_INIT | |
417 | bool "Skip calls to certain low level initialization functions" | |
a2ac2b96 TR |
418 | help |
419 | If enabled, then certain low level initializations (like setting up | |
420 | the memory controller) are omitted and/or U-Boot does not relocate | |
421 | itself into RAM. | |
422 | Normally this variable MUST NOT be defined. The only exception is | |
423 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
424 | debugger which performs these initializations itself. | |
425 | ||
426 | config SPL_SKIP_LOWLEVEL_INIT | |
c394e8d0 HS |
427 | bool "Skip calls to certain low level initialization functions in SPL" |
428 | depends on SPL | |
a2ac2b96 TR |
429 | help |
430 | If enabled, then certain low level initializations (like setting up | |
431 | the memory controller) are omitted and/or U-Boot does not relocate | |
432 | itself into RAM. | |
433 | Normally this variable MUST NOT be defined. The only exception is | |
434 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
435 | debugger which performs these initializations itself. | |
436 | ||
437 | config TPL_SKIP_LOWLEVEL_INIT | |
c394e8d0 | 438 | bool "Skip calls to certain low level initialization functions in TPL" |
a2ac2b96 TR |
439 | depends on SPL && ARM |
440 | help | |
441 | If enabled, then certain low level initializations (like setting up | |
442 | the memory controller) are omitted and/or U-Boot does not relocate | |
443 | itself into RAM. | |
444 | Normally this variable MUST NOT be defined. The only exception is | |
445 | when U-Boot is loaded (to RAM) by some other boot loader or by a | |
446 | debugger which performs these initializations itself. | |
447 | ||
448 | config SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 449 | bool "Skip call to lowlevel_init during early boot ONLY" |
a2ac2b96 TR |
450 | depends on ARM |
451 | help | |
452 | This allows just the call to lowlevel_init() to be skipped. The | |
453 | normal CP15 init (such as enabling the instruction cache) is still | |
454 | performed. | |
455 | ||
456 | config SPL_SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 457 | bool "Skip call to lowlevel_init during early SPL boot ONLY" |
a2ac2b96 TR |
458 | depends on SPL && ARM |
459 | help | |
460 | This allows just the call to lowlevel_init() to be skipped. The | |
461 | normal CP15 init (such as enabling the instruction cache) is still | |
462 | performed. | |
463 | ||
464 | config TPL_SKIP_LOWLEVEL_INIT_ONLY | |
c394e8d0 | 465 | bool "Skip call to lowlevel_init during early TPL boot ONLY" |
a2ac2b96 TR |
466 | depends on TPL && ARM |
467 | help | |
468 | This allows just the call to lowlevel_init() to be skipped. The | |
469 | normal CP15 init (such as enabling the instruction cache) is still | |
470 | performed. | |
471 | ||
c394e8d0 HS |
472 | endmenu |
473 | ||
8c778f78 TR |
474 | config SYS_HAS_NONCACHED_MEMORY |
475 | bool "Enable reserving a non-cached memory area for drivers" | |
476 | depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) | |
477 | help | |
478 | This is useful for drivers that would otherwise require a lot of | |
479 | explicit cache maintenance. For some drivers it's also impossible to | |
480 | properly maintain the cache. For example if the regions that need to | |
481 | be flushed are not a multiple of the cache-line size, *and* padding | |
482 | cannot be allocated between the regions to align them (i.e. if the | |
483 | HW requires a contiguous array of regions, and the size of each | |
484 | region is not cache-aligned), then a flush of one region may result | |
485 | in overwriting data that hardware has written to another region in | |
486 | the same cache-line. This can happen for example in network drivers | |
487 | where descriptors for buffers are typically smaller than the CPU | |
488 | cache-line (e.g. 16 bytes vs. 32 or 64 bytes). | |
489 | ||
490 | config SYS_NONCACHED_MEMORY | |
491 | hex "Size in bytes of the non-cached memory area" | |
492 | depends on SYS_HAS_NONCACHED_MEMORY | |
493 | default 0x100000 | |
494 | help | |
495 | Size of non-cached memory area. This area of memory will be typically | |
496 | located right below the malloc() area and mapped uncached in the MMU. | |
497 | ||
51631259 MY |
498 | source "arch/arc/Kconfig" |
499 | source "arch/arm/Kconfig" | |
51631259 MY |
500 | source "arch/m68k/Kconfig" |
501 | source "arch/microblaze/Kconfig" | |
502 | source "arch/mips/Kconfig" | |
51631259 | 503 | source "arch/nios2/Kconfig" |
51631259 MY |
504 | source "arch/powerpc/Kconfig" |
505 | source "arch/sandbox/Kconfig" | |
506 | source "arch/sh/Kconfig" | |
51631259 | 507 | source "arch/x86/Kconfig" |
c978b524 | 508 | source "arch/xtensa/Kconfig" |
068feb9b | 509 | source "arch/riscv/Kconfig" |
c6c0e56f | 510 | |
d622b089 TR |
511 | if ARM || M68K || PPC |
512 | ||
513 | source "arch/Kconfig.nxp" | |
514 | ||
515 | endif | |
516 | ||
c6c0e56f | 517 | source "board/keymile/Kconfig" |
89e81e6c | 518 | |
10fd6d64 | 519 | if MIPS || MICROBLAZE |
89e81e6c MS |
520 | |
521 | choice | |
522 | prompt "Endianness selection" | |
523 | help | |
524 | Some MIPS boards can be configured for either little or big endian | |
525 | byte order. These modes require different U-Boot images. In general there | |
526 | is one preferred byteorder for a particular system but some systems are | |
527 | just as commonly used in the one or the other endianness. | |
528 | ||
529 | config SYS_BIG_ENDIAN | |
530 | bool "Big endian" | |
10fd6d64 | 531 | depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE |
89e81e6c MS |
532 | |
533 | config SYS_LITTLE_ENDIAN | |
534 | bool "Little endian" | |
10fd6d64 | 535 | depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE |
89e81e6c MS |
536 | |
537 | endchoice | |
538 | ||
539 | endif |