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armv8: ls1028a: enable workaround for USB erratum A-008997
[thirdparty/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / soc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
b991b981 2/*
9f3183d2 3 * Copyright 2014-2015 Freescale Semiconductor
b991b981
SW		 4 */
5
6#include <common.h>
63b2316c 7#include <fsl_immap.h>
b991b981 8#include <fsl_ifc.h>
b392a6d4 9#include <asm/arch/fsl_serdes.h>
9f3183d2 10#include <asm/arch/soc.h>
d746fef4 11#include <asm/io.h>
b2d5ac59 12#include <asm/global_data.h>
b4017364 13#include <asm/arch-fsl-layerscape/config.h>
9add5a4b 14#include <asm/arch-fsl-layerscape/ns_access.h>
3cb4fe65 15#include <asm/arch-fsl-layerscape/fsl_icid.h>
b392a6d4 16#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
341238fd 17#include <fsl_csu.h>
b392a6d4 18#endif
b7f2bbff 19#ifdef CONFIG_SYS_FSL_DDR
074596c0
SL		 20#include <fsl_ddr_sdram.h>
21#include <fsl_ddr.h>
b7f2bbff 22#endif
d0412885
AB		 23#ifdef CONFIG_CHAIN_OF_TRUST
24#include <fsl_validate.h>
25#endif
6d9b82d0 26#include <fsl_immap.h>
2141d250
PG		 27#ifdef CONFIG_TFABOOT
28#include <environment.h>
29DECLARE_GLOBAL_DATA_PTR;
30#endif
b2d5ac59 31
3c1d218a
YS		 32bool soc_has_dp_ddr(void)
33{
34 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
35 u32 svr = gur_in32(&gur->svr);
36
9ae836cd
PJ		 37 /* LS2085A, LS2088A, LS2048A has DP_DDR */
38 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
39 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
40 (SVR_SOC_VER(svr) == SVR_LS2048A))
3c1d218a
YS		 41 return true;
42
43 return false;
44}
45
46bool soc_has_aiop(void)
47{
48 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
49 u32 svr = gur_in32(&gur->svr);
50
51 /* LS2085A has AIOP */
49cdce16 52 if (SVR_SOC_VER(svr) == SVR_LS2085A)
3c1d218a
YS		 53 return true;
54
55 return false;
56}
57
2ab1553f
RW		 58static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
59{
60 scfg_clrsetbits32(scfg + offset / 4,
61 0xF << 6,
62 SCFG_USB_TXVREFTUNE << 6);
63}
64
65static void erratum_a009008(void)
66{
67#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
68 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
2a8a3539 69
819163c4
RW		 70#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
71 defined(CONFIG_ARCH_LS1012A)
2ab1553f 72 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
819163c4 73#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
2ab1553f
RW		 74 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
75 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
819163c4 76#endif
2ab1553f
RW		 77#elif defined(CONFIG_ARCH_LS2080A)
78 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
79#endif
80#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
81}
82
2a8a3539
RW		 83static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
84{
85 scfg_clrbits32(scfg + offset / 4,
86 SCFG_USB_SQRXTUNE_MASK << 23);
87}
88
89static void erratum_a009798(void)
90{
91#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
92 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
93
819163c4
RW		 94#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
95 defined(CONFIG_ARCH_LS1012A)
2a8a3539 96 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
819163c4 97#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
2a8a3539
RW		 98 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
99 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
819163c4 100#endif
2a8a3539
RW		 101#elif defined(CONFIG_ARCH_LS2080A)
102 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
103#endif
104#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
105}
106
819163c4
RW		 107#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
108 defined(CONFIG_ARCH_LS1012A)
9d1cd910
RW		 109static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
110{
111 scfg_clrsetbits32(scfg + offset / 4,
112 0x7F << 9,
113 SCFG_USB_PCSTXSWINGFULL << 9);
114}
115#endif
116
117static void erratum_a008997(void)
118{
119#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
819163c4
RW		 120#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
121 defined(CONFIG_ARCH_LS1012A)
9d1cd910
RW		 122 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
123
124 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
819163c4 125#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
9d1cd910
RW		 126 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
127 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
128#endif
3458a419
RW		 129#elif defined(CONFIG_ARCH_LS1028A)
130 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
131 0x7F << 11,
132 DCSR_USB_PCSTXSWINGFULL << 11);
819163c4 133#endif
9d1cd910
RW		 134#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
135}
136
819163c4
RW		 137#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
138 defined(CONFIG_ARCH_LS1012A)
15d59b53
RW		 139
140#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
141 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
142 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
143 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
144 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
145
7458c5e6 146#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
15d59b53
RW		 147
148#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
149 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
150 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
151 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
152 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
153
154#endif
155
156static void erratum_a009007(void)
157{
819163c4
RW		 158#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
159 defined(CONFIG_ARCH_LS1012A)
15d59b53
RW		 160 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
161
162 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
819163c4 163#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
15d59b53
RW		 164 usb_phy = (void __iomem *)SCFG_USB_PHY2;
165 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
166
167 usb_phy = (void __iomem *)SCFG_USB_PHY3;
168 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
819163c4 169#endif
7458c5e6 170#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
15d59b53
RW		 171 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
172
173 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
174 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
175#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
176}
177
40836e21 178#if defined(CONFIG_FSL_LSCH3)
000f4e76
YY		 179/*
180 * This erratum requires setting a value to eddrtqcr1 to
181 * optimal the DDR performance.
182 */
183static void erratum_a008336(void)
184{
40836e21 185#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
000f4e76
YY		 186 u32 *eddrtqcr1;
187
000f4e76
YY		 188#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
189 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
1a87c24f
SL		 190 if (fsl_ddr_get_version(0) == 0x50200)
191 out_le32(eddrtqcr1, 0x63b30002);
000f4e76
YY		 192#endif
193#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
194 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
1a87c24f
SL		 195 if (fsl_ddr_get_version(0) == 0x50200)
196 out_le32(eddrtqcr1, 0x63b30002);
000f4e76
YY		 197#endif
198#endif
199}
200
201/*
202 * This erratum requires a register write before being Memory
203 * controller 3 being enabled.
204 */
205static void erratum_a008514(void)
206{
40836e21 207#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
000f4e76
YY		 208 u32 *eddrtqcr1;
209
000f4e76
YY		 210#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
211 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
212 out_le32(eddrtqcr1, 0x63b20002);
213#endif
214#endif
215}
b4017364
PK		 216#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
217#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
218
219static unsigned long get_internval_val_mhz(void)
220{
00caae6d 221 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
b4017364
PK		 222 /*
223 * interval is the number of platform cycles(MHz) between
224 * wake up events generated by EPU.
225 */
226 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
227
228 if (interval)
229 interval_mhz = simple_strtoul(interval, NULL, 10);
230
231 return interval_mhz;
232}
233
234void erratum_a009635(void)
235{
236 u32 val;
237 unsigned long interval_mhz = get_internval_val_mhz();
238
239 if (!interval_mhz)
240 return;
241
242 val = in_le32(DCSR_CGACRE5);
243 writel(val | 0x00000200, DCSR_CGACRE5);
244
245 val = in_le32(EPU_EPCMPR5);
246 writel(interval_mhz, EPU_EPCMPR5);
247 val = in_le32(EPU_EPCCR5);
248 writel(val | 0x82820000, EPU_EPCCR5);
249 val = in_le32(EPU_EPSMCR5);
250 writel(val | 0x002f0000, EPU_EPSMCR5);
251 val = in_le32(EPU_EPECR5);
252 writel(val | 0x20000000, EPU_EPECR5);
253 val = in_le32(EPU_EPGCR);
254 writel(val | 0x80000000, EPU_EPGCR);
255}
256#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
257
b2d5ac59
SW		 258static void erratum_rcw_src(void)
259{
faed6bde 260#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
b2d5ac59
SW		 261 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
262 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
263 u32 val;
264
265 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
266 val &= ~DCFG_PORSR1_RCW_SRC;
267 val |= DCFG_PORSR1_RCW_SRC_NOR;
268 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
269#endif
270}
271
ab10d73d
YS		 272#define I2C_DEBUG_REG 0x6
273#define I2C_GLITCH_EN 0x8
274/*
275 * This erratum requires setting glitch_en bit to enable
276 * digital glitch filter to improve clock stability.
277 */
dd48f0bf 278#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d
YS		 279static void erratum_a009203(void)
280{
ab10d73d 281#ifdef CONFIG_SYS_I2C
0d7f1ae0 282 u8 __iomem *ptr;
ab10d73d
YS		 283#ifdef I2C1_BASE_ADDR
284 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
285
286 writeb(I2C_GLITCH_EN, ptr);
287#endif
288#ifdef I2C2_BASE_ADDR
289 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
290
291 writeb(I2C_GLITCH_EN, ptr);
292#endif
293#ifdef I2C3_BASE_ADDR
294 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
295
296 writeb(I2C_GLITCH_EN, ptr);
297#endif
298#ifdef I2C4_BASE_ADDR
299 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
300
301 writeb(I2C_GLITCH_EN, ptr);
302#endif
303#endif
304}
dd48f0bf 305#endif
40836e21 306
4a97a0c9
SJ		 307void bypass_smmu(void)
308{
309 u32 val;
310 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
311 out_le32(SMMU_SCR0, val);
312 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
313 out_le32(SMMU_NSCR0, val);
314}
b991b981
SW		 315void fsl_lsch3_early_init_f(void)
316{
b2d5ac59 317 erratum_rcw_src();
e45ff0ce 318#ifdef CONFIG_FSL_IFC
b991b981 319 init_early_memctl_regs(); /* tighten IFC timing */
e45ff0ce 320#endif
dd48f0bf 321#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
ab10d73d 322 erratum_a009203();
dd48f0bf 323#endif
000f4e76
YY		 324 erratum_a008514();
325 erratum_a008336();
2ab1553f 326 erratum_a009008();
2a8a3539 327 erratum_a009798();
9d1cd910 328 erratum_a008997();
15d59b53 329 erratum_a009007();
4a97a0c9
SJ		 330#ifdef CONFIG_CHAIN_OF_TRUST
331 /* In case of Secure Boot, the IBR configures the SMMU
332 * to allow only Secure transactions.
333 * SMMU must be reset in bypass mode.
334 * Set the ClientPD bit and Clear the USFCFG Bit
335 */
336 if (fsl_check_boot_mode_secure() == 1)
337 bypass_smmu();
338#endif
b991b981 339}
8281c58f 340
a1f95ff7
RB		 341/* Get VDD in the unit mV from voltage ID */
342int get_core_volt_from_fuse(void)
343{
344 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
345 int vdd;
346 u32 fusesr;
347 u8 vid;
348
349 /* get the voltage ID from fuse status register */
350 fusesr = in_le32(&gur->dcfg_fusesr);
351 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
352 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
353 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
354 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
355 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
356 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
357 }
358 debug("%s: VID = 0x%x\n", __func__, vid);
359 switch (vid) {
360 case 0x00: /* VID isn't supported */
361 vdd = -EINVAL;
362 debug("%s: The VID feature is not supported\n", __func__);
363 break;
364 case 0x08: /* 0.9V silicon */
365 vdd = 900;
366 break;
367 case 0x10: /* 1.0V silicon */
368 vdd = 1000;
369 break;
370 default: /* Other core voltage */
371 vdd = -EINVAL;
372 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
373 break;
374 }
375 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
376
377 return vdd;
378}
379
22a44d08 380#elif defined(CONFIG_FSL_LSCH2)
989c5f0a 381
0d6faf2b
MH		 382static void erratum_a009929(void)
383{
384#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
385 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
386 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
387 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
388
389 rstrqmr1 |= 0x00000400;
390 gur_out32(&gur->rstrqmr1, rstrqmr1);
391 writel(0x01000000, dcsr_cop_ccp);
392#endif
393}
394
bbc8e053
MH		 395/*
396 * This erratum requires setting a value to eddrtqcr1 to optimal
397 * the DDR performance. The eddrtqcr1 register is in SCFG space
398 * of LS1043A and the offset is 0x157_020c.
399 */
400#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
401 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
402#error A009660 and A008514 can not be both enabled.
403#endif
404
405static void erratum_a009660(void)
406{
407#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
408 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
409 out_be32(eddrtqcr1, 0x63b20042);
410#endif
411}
412
074596c0
SL		 413static void erratum_a008850_early(void)
414{
415#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
416 /* part 1 of 2 */
63b2316c
AK		 417 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
418 CONFIG_SYS_CCI400_OFFSET);
074596c0
SL		 419 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
420
399e2bb6
YS		 421 /* Skip if running at lower exception level */
422 if (current_el() < 3)
423 return;
424
074596c0
SL		 425 /* disables propagation of barrier transactions to DDRC from CCI400 */
426 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
427
428 /* disable the re-ordering in DDRC */
429 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
430#endif
431}
432
433void erratum_a008850_post(void)
434{
435#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
436 /* part 2 of 2 */
63b2316c
AK		 437 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
438 CONFIG_SYS_CCI400_OFFSET);
074596c0
SL		 439 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
440 u32 tmp;
441
399e2bb6
YS		 442 /* Skip if running at lower exception level */
443 if (current_el() < 3)
444 return;
445
074596c0
SL		 446 /* enable propagation of barrier transactions to DDRC from CCI400 */
447 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
448
449 /* enable the re-ordering in DDRC */
450 tmp = ddr_in32(&ddr->eor);
451 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
452 ddr_out32(&ddr->eor, tmp);
453#endif
454}
455
b392a6d4
HZ		 456#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
457void erratum_a010315(void)
458{
459 int i;
460
461 for (i = PCIE1; i <= PCIE4; i++)
462 if (!is_serdes_configured(i)) {
463 debug("PCIe%d: disabled all R/W permission!\n", i);
464 set_pcie_ns_access(i, 0);
465 }
466}
467#endif
468
0ea3671d
HZ		 469static void erratum_a010539(void)
470{
471#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
472 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
473 u32 porsr1;
474
475 porsr1 = in_be32(&gur->porsr1);
476 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
477 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
478 porsr1);
8b40f229 479 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
0ea3671d
HZ		 480#endif
481}
482
031acdba
HZ		 483/* Get VDD in the unit mV from voltage ID */
484int get_core_volt_from_fuse(void)
485{
486 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
487 int vdd;
488 u32 fusesr;
489 u8 vid;
490
491 fusesr = in_be32(&gur->dcfg_fusesr);
492 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
493 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
494 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
495 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
496 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
497 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
498 }
499 debug("%s: VID = 0x%x\n", __func__, vid);
500 switch (vid) {
501 case 0x00: /* VID isn't supported */
502 vdd = -EINVAL;
503 debug("%s: The VID feature is not supported\n", __func__);
504 break;
505 case 0x08: /* 0.9V silicon */
506 vdd = 900;
507 break;
508 case 0x10: /* 1.0V silicon */
509 vdd = 1000;
510 break;
511 default: /* Other core voltage */
512 vdd = -EINVAL;
513 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
514 break;
515 }
516 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
517
518 return vdd;
519}
520
521__weak int board_switch_core_volt(u32 vdd)
522{
523 return 0;
524}
525
526static int setup_core_volt(u32 vdd)
527{
528 return board_setup_core_volt(vdd);
529}
530
531#ifdef CONFIG_SYS_FSL_DDR
532static void ddr_enable_0v9_volt(bool en)
533{
534 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
535 u32 tmp;
536
537 tmp = ddr_in32(&ddr->ddr_cdr1);
538
539 if (en)
540 tmp |= DDR_CDR1_V0PT9_EN;
541 else
542 tmp &= ~DDR_CDR1_V0PT9_EN;
543
544 ddr_out32(&ddr->ddr_cdr1, tmp);
545}
546#endif
547
548int setup_chip_volt(void)
549{
550 int vdd;
551
552 vdd = get_core_volt_from_fuse();
553 /* Nothing to do for silicons doesn't support VID */
554 if (vdd < 0)
555 return vdd;
556
557 if (setup_core_volt(vdd))
558 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
559#ifdef CONFIG_SYS_HAS_SERDES
560 if (setup_serdes_volt(vdd))
561 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
562#endif
563
564#ifdef CONFIG_SYS_FSL_DDR
565 if (vdd == 900)
566 ddr_enable_0v9_volt(true);
567#endif
568
569 return 0;
570}
571
c4dc68b0
CJ		 572#ifdef CONFIG_FSL_PFE
573void init_pfe_scfg_dcfg_regs(void)
574{
575 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
576 u32 ecccr2;
577
578 out_be32(&scfg->pfeasbcr,
579 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
580 out_be32(&scfg->pfebsbcr,
581 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
582
583 /* CCI-400 QoS settings for PFE */
584 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
585 | SCFG_WR_QOS1_PFE2_QOS));
586 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
587 | SCFG_RD_QOS1_PFE2_QOS));
588
589 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
590 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
591 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
592}
593#endif
594
8281c58f
MH		 595void fsl_lsch2_early_init_f(void)
596{
63b2316c
AK		 597 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
598 CONFIG_SYS_CCI400_OFFSET);
70f959c3 599 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
8281c58f 600
341238fd
HZ		 601#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
602 enable_layerscape_ns_access();
603#endif
604
8281c58f
MH		 605#ifdef CONFIG_FSL_IFC
606 init_early_memctl_regs(); /* tighten IFC timing */
607#endif
608
258b8c93 609#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
166ef1e9
GQ		 610 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
611#endif
70f959c3
AB		 612 /* Make SEC reads and writes snoopable */
613 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
4de6ce15
TY		 614 SCFG_SNPCNFGCR_SECWRSNP |
615 SCFG_SNPCNFGCR_SATARDSNP |
616 SCFG_SNPCNFGCR_SATAWRSNP);
70f959c3 617
8281c58f
MH		 618 /*
619 * Enable snoop requests and DVM message requests for
620 * Slave insterface S4 (A53 core cluster)
621 */
399e2bb6
YS		 622 if (current_el() == 3) {
623 out_le32(&cci->slave[4].snoop_ctrl,
624 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
625 }
0d6faf2b 626
9add5a4b
RW		 627 /*
628 * Program Central Security Unit (CSU) to grant access
629 * permission for USB 2.0 controller
630 */
631#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
632 if (current_el() == 3)
633 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
634#endif
0d6faf2b 635 /* Erratum */
074596c0 636 erratum_a008850_early(); /* part 1 of 2 */
0d6faf2b 637 erratum_a009929();
bbc8e053 638 erratum_a009660();
0ea3671d 639 erratum_a010539();
2ab1553f 640 erratum_a009008();
2a8a3539 641 erratum_a009798();
9d1cd910 642 erratum_a008997();
15d59b53 643 erratum_a009007();
3cb4fe65 644
dc29a4c1 645#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
3cb4fe65
LT		 646 set_icids();
647#endif
8281c58f 648}
9f3183d2 649#endif
b2d5ac59 650
dd2ad2f1
YY		 651#ifdef CONFIG_QSPI_AHB_INIT
652/* Enable 4bytes address support and fast read */
653int qspi_ahb_init(void)
654{
655 u32 *qspi_lut, lut_key, *qspi_key;
656
657 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
658 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
659
660 lut_key = in_be32(qspi_key);
661
662 if (lut_key == 0x5af05af0) {
663 /* That means the register is BE */
664 out_be32(qspi_key, 0x5af05af0);
665 /* Unlock the lut table */
666 out_be32(qspi_key + 1, 0x00000002);
667 out_be32(qspi_lut, 0x0820040c);
668 out_be32(qspi_lut + 1, 0x1c080c08);
669 out_be32(qspi_lut + 2, 0x00002400);
670 /* Lock the lut table */
671 out_be32(qspi_key, 0x5af05af0);
672 out_be32(qspi_key + 1, 0x00000001);
673 } else {
674 /* That means the register is LE */
675 out_le32(qspi_key, 0x5af05af0);
676 /* Unlock the lut table */
677 out_le32(qspi_key + 1, 0x00000002);
678 out_le32(qspi_lut, 0x0820040c);
679 out_le32(qspi_lut + 1, 0x1c080c08);
680 out_le32(qspi_lut + 2, 0x00002400);
681 /* Lock the lut table */
682 out_le32(qspi_key, 0x5af05af0);
683 out_le32(qspi_key + 1, 0x00000001);
684 }
685
686 return 0;
687}
688#endif
689
2141d250 690#ifdef CONFIG_TFABOOT
d23da2ae 691#define MAX_BOOTCMD_SIZE 512
2141d250
PG		 692
693int fsl_setenv_bootcmd(void)
694{
695 int ret;
696 enum boot_src src = get_boot_src();
697 char bootcmd_str[MAX_BOOTCMD_SIZE];
698
699 switch (src) {
700#ifdef IFC_NOR_BOOTCOMMAND
701 case BOOT_SOURCE_IFC_NOR:
702 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
703 break;
704#endif
705#ifdef QSPI_NOR_BOOTCOMMAND
706 case BOOT_SOURCE_QSPI_NOR:
707 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
708 break;
709#endif
710#ifdef XSPI_NOR_BOOTCOMMAND
711 case BOOT_SOURCE_XSPI_NOR:
712 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
713 break;
714#endif
715#ifdef IFC_NAND_BOOTCOMMAND
716 case BOOT_SOURCE_IFC_NAND:
717 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
718 break;
719#endif
720#ifdef QSPI_NAND_BOOTCOMMAND
721 case BOOT_SOURCE_QSPI_NAND:
722 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
723 break;
724#endif
725#ifdef XSPI_NAND_BOOTCOMMAND
726 case BOOT_SOURCE_XSPI_NAND:
727 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
728 break;
729#endif
730#ifdef SD_BOOTCOMMAND
731 case BOOT_SOURCE_SD_MMC:
732 sprintf(bootcmd_str, SD_BOOTCOMMAND);
733 break;
734#endif
735#ifdef SD2_BOOTCOMMAND
736 case BOOT_SOURCE_SD_MMC2:
737 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
738 break;
739#endif
740 default:
741#ifdef QSPI_NOR_BOOTCOMMAND
742 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
743#endif
744 break;
745 }
746
747 ret = env_set("bootcmd", bootcmd_str);
748 if (ret) {
749 printf("Failed to set bootcmd: ret = %d\n", ret);
750 return ret;
751 }
752 return 0;
753}
ade32bb4
PG		 754
755int fsl_setenv_mcinitcmd(void)
756{
757 int ret = 0;
758 enum boot_src src = get_boot_src();
759
760 switch (src) {
761#ifdef IFC_MC_INIT_CMD
762 case BOOT_SOURCE_IFC_NAND:
763 case BOOT_SOURCE_IFC_NOR:
764 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
765 break;
766#endif
767#ifdef QSPI_MC_INIT_CMD
768 case BOOT_SOURCE_QSPI_NAND:
769 case BOOT_SOURCE_QSPI_NOR:
770 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
771 break;
772#endif
773#ifdef XSPI_MC_INIT_CMD
774 case BOOT_SOURCE_XSPI_NAND:
775 case BOOT_SOURCE_XSPI_NOR:
776 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
777 break;
778#endif
779#ifdef SD_MC_INIT_CMD
780 case BOOT_SOURCE_SD_MMC:
781 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
782 break;
783#endif
784#ifdef SD2_MC_INIT_CMD
785 case BOOT_SOURCE_SD_MMC2:
786 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
787 break;
788#endif
789 default:
790#ifdef QSPI_MC_INIT_CMD
791 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
792#endif
793 break;
794 }
795
796 if (ret) {
797 printf("Failed to set mcinitcmd: ret = %d\n", ret);
798 return ret;
799 }
800 return 0;
801}
2141d250
PG		 802#endif
803
9f3183d2
MH		 804#ifdef CONFIG_BOARD_LATE_INIT
805int board_late_init(void)
b2d5ac59 806{
d0412885
AB		 807#ifdef CONFIG_CHAIN_OF_TRUST
808 fsl_setenv_chain_of_trust();
809#endif
2141d250
PG		 810#ifdef CONFIG_TFABOOT
811 /*
812 * check if gd->env_addr is default_environment; then setenv bootcmd
ade32bb4 813 * and mcinitcmd.
2141d250 814 */
ade32bb4 815 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
2141d250 816 fsl_setenv_bootcmd();
ade32bb4
PG		 817 fsl_setenv_mcinitcmd();
818 }
d23da2ae
RB		 819
820 /*
821 * If the boot mode is secure, default environment is not present then
822 * setenv command needs to be run by default
823 */
824#ifdef CONFIG_CHAIN_OF_TRUST
825 if ((fsl_check_boot_mode_secure() == 1)) {
826 fsl_setenv_bootcmd();
827 fsl_setenv_mcinitcmd();
828 }
829#endif
2141d250 830#endif
dd2ad2f1
YY		 831#ifdef CONFIG_QSPI_AHB_INIT
832 qspi_ahb_init();
833#endif
989c5f0a 834
9f3183d2 835 return 0;
b2d5ac59
SW		 836}
837#endif
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