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4549e789 | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
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2 | /* |
3 | * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH | |
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4 | */ |
5 | ||
5aefa4af HS |
6 | #include "rk3368-u-boot.dtsi" |
7 | ||
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8 | / { |
9 | config { | |
10 | u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ | |
11 | u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ | |
12 | }; | |
13 | ||
14 | chosen { | |
15 | stdout-path = "serial0:115200n8"; | |
16 | u-boot,spl-boot-order = &emmc, &sdmmc; | |
17 | }; | |
18 | ||
70190f82 SG |
19 | smbios { |
20 | compatible = "u-boot,sysinfo-smbios"; | |
21 | ||
22 | smbios { | |
23 | system { | |
24 | manufacturer = "rockchip"; | |
25 | product = "sheep_rk3368"; | |
26 | }; | |
27 | ||
28 | baseboard { | |
29 | manufacturer = "rockchip"; | |
30 | product = "sheep_rk3368"; | |
31 | }; | |
32 | ||
33 | chassis { | |
34 | manufacturer = "rockchip"; | |
35 | product = "sheep_rk3368"; | |
36 | }; | |
37 | }; | |
38 | }; | |
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39 | }; |
40 | ||
ba421b96 HS |
41 | &gpio2 { |
42 | u-boot,dm-pre-reloc; | |
43 | }; | |
44 | ||
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45 | &pinctrl { |
46 | u-boot,dm-pre-reloc; | |
47 | }; | |
48 | ||
49 | &service_msch { | |
50 | u-boot,dm-pre-reloc; | |
51 | }; | |
52 | ||
53 | &dmc { | |
54 | u-boot,dm-pre-reloc; | |
55 | ||
56 | /* | |
57 | * Validation of throughput using SPEC2000 shows the following | |
58 | * relative performance for the different memory schedules: | |
59 | * - CBDR: 30.1 | |
60 | * - CBRD: 29.8 | |
61 | * - CRBD: 29.9 | |
62 | * Note that the best performance for any given application workload | |
63 | * may vary from the default configured here (e.g. 164.gzip is fastest | |
64 | * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). | |
65 | * | |
66 | * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for | |
67 | * details on the 'rockchip,memory-schedule' property and how it | |
68 | * affects the physical-address to device-address mapping. | |
69 | */ | |
70 | rockchip,memory-schedule = <DMC_MSCH_CBDR>; | |
71 | rockchip,ddr-frequency = <800000000>; | |
72 | rockchip,ddr-speed-bin = <DDR3_1600K>; | |
73 | ||
74 | status = "okay"; | |
75 | }; | |
76 | ||
77 | &pmugrf { | |
78 | u-boot,dm-pre-reloc; | |
79 | }; | |
80 | ||
81 | &sgrf { | |
82 | u-boot,dm-pre-reloc; | |
83 | }; | |
84 | ||
85 | &cru { | |
86 | u-boot,dm-pre-reloc; | |
87 | }; | |
88 | ||
89 | &grf { | |
90 | u-boot,dm-pre-reloc; | |
91 | }; | |
92 | ||
93 | &uart0 { | |
94 | u-boot,dm-pre-reloc; | |
95 | }; | |
96 | ||
97 | &emmc { | |
75ff0578 | 98 | u-boot,dm-spl; |
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99 | }; |
100 | ||
101 | &sdmmc { | |
75ff0578 | 102 | u-boot,dm-spl; |
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103 | }; |
104 | ||
105 | &spi1 { | |
75ff0578 | 106 | u-boot,dm-spl; |
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107 | |
108 | spiflash: w25q32dw@0 { | |
75ff0578 | 109 | u-boot,dm-spl; |
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110 | }; |
111 | }; | |
112 | ||
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113 | &timer0 { |
114 | u-boot,dm-pre-reloc; | |
115 | clock-frequency = <24000000>; | |
f041176c | 116 | status = "okay"; |
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117 | }; |
118 | ||
4d02d206 | 119 |