projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| b43c17cb MP |
2 | /* |
| 3 | * hardware_am33xx.h | |
| 4 | * | |
| 5 | * AM33xx hardware specific header | |
| 6 | * | |
| 7 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ | |
| b43c17cb MP |
8 | */ |
| 9 | ||
| 10 | #ifndef __AM33XX_HARDWARE_AM33XX_H | |
| 11 | #define __AM33XX_HARDWARE_AM33XX_H | |
| 12 | ||
| 8b029f22 MP |
13 | /* Module base addresses */ |
| 14 | ||
| 15 | /* UART Base Address */ | |
| 16 | #define UART0_BASE 0x44E09000 | |
| 48c7f771 LCR |
17 | #define UART1_BASE 0x48022000 |
| 18 | #define UART2_BASE 0x48024000 | |
| 19 | #define UART3_BASE 0x481A6000 | |
| 20 | #define UART4_BASE 0x481A8000 | |
| 21 | #define UART5_BASE 0x481AA000 | |
| 8b029f22 MP |
22 | |
| 23 | /* GPIO Base address */ | |
| 24 | #define GPIO2_BASE 0x481AC000 | |
| 25 | ||
| 26 | /* Watchdog Timer */ | |
| 27 | #define WDT_BASE 0x44E35000 | |
| 28 | ||
| 29 | /* Control Module Base Address */ | |
| 30 | #define CTRL_BASE 0x44E10000 | |
| 31 | #define CTRL_DEVICE_BASE 0x44E10600 | |
| 32 | ||
| 33 | /* PRCM Base Address */ | |
| 34 | #define PRCM_BASE 0x44E00000 | |
| c06e498a LV |
35 | #define CM_PER 0x44E00000 |
| 36 | #define CM_WKUP 0x44E00400 | |
| 7ca1b2a2 LV |
37 | #define CM_DPLL 0x44E00500 |
| 38 | #define CM_RTC 0x44E00800 | |
| c06e498a LV |
39 | |
| 40 | #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) | |
| 41 | #define PRM_RSTST (PRM_RSTCTRL + 8) | |
| 8b029f22 | 42 | |
| b43c17cb MP |
43 | /* VTP Base address */ |
| 44 | #define VTP0_CTRL_ADDR 0x44E10E0C | |
| dcf846d5 | 45 | #define VTP1_CTRL_ADDR 0x48140E10 |
| fc46bae2 | 46 | #define PRM_DEVICE_INST 0x44E00F00 |
| b43c17cb MP |
47 | |
| 48 | /* DDR Base address */ | |
| 49 | #define DDR_PHY_CMD_ADDR 0x44E12000 | |
| 50 | #define DDR_PHY_DATA_ADDR 0x44E120C8 | |
| dcf846d5 TA |
51 | #define DDR_PHY_CMD_ADDR2 0x47C0C800 |
| 52 | #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 | |
| b43c17cb MP |
53 | #define DDR_DATA_REGS_NR 2 |
| 54 | ||
| dcf846d5 TA |
55 | #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) |
| 56 | #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE | |
| 57 | ||
| 8b029f22 MP |
58 | /* CPSW Config space */ |
| 59 | #define CPSW_MDIO_BASE 0x4A101000 | |
| 60 | ||
| 61 | /* RTC base address */ | |
| 62 | #define RTC_BASE 0x44E3E000 | |
| 63 | ||
| c06e498a LV |
64 | /* OTG */ |
| 65 | #define USB0_OTG_BASE 0x47401000 | |
| 66 | #define USB1_OTG_BASE 0x47401800 | |
| 67 | ||
| 14c0158b HS |
68 | /* LCD Controller */ |
| 69 | #define LCD_CNTL_BASE 0x4830E000 | |
| 70 | ||
| 71 | /* PWMSS */ | |
| 72 | #define PWMSS0_BASE 0x48300000 | |
| 73 | #define AM33XX_ECAP0_BASE 0x48300100 | |
| f61c9bcd | 74 | #define AM33XX_EPWM_BASE 0x48300200 |
| 14c0158b | 75 | |
| b43c17cb | 76 | #endif /* __AM33XX_HARDWARE_AM33XX_H */ |