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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2f78eae5 YS |
2 | /* |
3 | * LayerScape Internal Memory Map | |
4 | * | |
1eba723c | 5 | * Copyright 2017-2019 NXP |
2f78eae5 | 6 | * Copyright 2014 Freescale Semiconductor, Inc. |
2f78eae5 YS |
7 | */ |
8 | ||
9f3183d2 | 9 | #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ |
2f78eae5 YS |
10 | #define __ARCH_FSL_LSCH3_IMMAP_H_ |
11 | ||
9f3183d2 MH |
12 | #define CONFIG_SYS_IMMR 0x01000000 |
13 | #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) | |
14 | #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) | |
15 | #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 | |
16 | #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) | |
17 | #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) | |
4909b89e PJ |
18 | #ifdef CONFIG_ARCH_LX2160A |
19 | #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) | |
20 | #else | |
9f3183d2 | 21 | #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) |
4909b89e | 22 | #endif |
9f3183d2 MH |
23 | #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) |
24 | #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) | |
25 | #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) | |
dd2ad2f1 | 26 | #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) |
9f3183d2 | 27 | #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) |
d6fdec21 | 28 | #ifndef CONFIG_NXP_LSCH3_2 |
9f3183d2 | 29 | #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) |
d6fdec21 | 30 | #endif |
9f3183d2 MH |
31 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) |
32 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) | |
f6b96ff6 PJ |
33 | #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 |
34 | #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 | |
9f3183d2 MH |
35 | #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ |
36 | 0x18A0) | |
a758177f | 37 | #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) |
f6a70b3a | 38 | #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) |
9f3183d2 MH |
39 | |
40 | #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) | |
41 | #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) | |
42 | #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) | |
43 | #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) | |
44 | ||
9f3183d2 MH |
45 | #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL |
46 | #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL | |
47 | #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL | |
48 | #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL | |
49 | ||
50 | #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) | |
51 | #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) | |
52 | #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) | |
53 | #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) | |
d6fdec21 PJ |
54 | #ifdef CONFIG_NXP_LSCH3_2 |
55 | #define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) | |
56 | #define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) | |
57 | #define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) | |
58 | #define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) | |
59 | #endif | |
5193405a PJ |
60 | #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) |
61 | #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) | |
62 | #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) | |
9f3183d2 | 63 | |
9729dc95 RB |
64 | #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) |
65 | #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) | |
9f3183d2 MH |
66 | |
67 | /* TZ Address Space Controller Definitions */ | |
68 | #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ | |
69 | #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ | |
70 | #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ | |
71 | #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ | |
72 | #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) | |
73 | #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) | |
74 | #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) | |
75 | #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) | |
76 | #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) | |
77 | #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) | |
78 | #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) | |
79 | #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) | |
80 | #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) | |
81 | ||
989c5f0a TY |
82 | /* SATA */ |
83 | #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) | |
84 | #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) | |
85 | ||
3808190a SJ |
86 | /* SFP */ |
87 | #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) | |
88 | ||
2827d647 | 89 | /* SEC */ |
e99d7193 AP |
90 | #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull |
91 | #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull | |
ef3f364a LT |
92 | #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET |
93 | #define FSL_SEC_JR1_OFFSET 0x07020000ull | |
94 | #define FSL_SEC_JR2_OFFSET 0x07030000ull | |
95 | #define FSL_SEC_JR3_OFFSET 0x07040000ull | |
e99d7193 AP |
96 | #define CONFIG_SYS_FSL_SEC_ADDR \ |
97 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) | |
98 | #define CONFIG_SYS_FSL_JR0_ADDR \ | |
99 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) | |
ef3f364a LT |
100 | #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) |
101 | #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) | |
102 | #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) | |
103 | #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) | |
2827d647 | 104 | |
4c417384 | 105 | #ifdef CONFIG_TFABOOT |
d6fdec21 | 106 | #ifdef CONFIG_NXP_LSCH3_2 |
4c417384 RB |
107 | /* RCW_SRC field in Power-On Reset Control Register 1 */ |
108 | #define RCW_SRC_MASK 0x07800000 | |
109 | #define RCW_SRC_BIT 23 | |
110 | ||
111 | /* CFG_RCW_SRC[3:0] */ | |
112 | #define RCW_SRC_TYPE_MASK 0x8 | |
113 | #define RCW_SRC_ADDR_OFFSET_8MB 0x800000 | |
114 | ||
115 | /* RCW SRC HARDCODED */ | |
116 | #define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */ | |
117 | ||
118 | #define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */ | |
119 | #define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */ | |
120 | #define RCW_SRC_I2C1_VAL 0xa /* 0xa */ | |
121 | #define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */ | |
122 | #define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */ | |
123 | #define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */ | |
124 | #define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */ | |
125 | #define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */ | |
126 | #else | |
127 | #define RCW_SRC_MASK (0xFF800000) | |
128 | #define RCW_SRC_BIT 23 | |
129 | /* CFG_RCW_SRC[6:0] */ | |
130 | #define RCW_SRC_TYPE_MASK (0x70) | |
131 | ||
132 | /* RCW SRC HARDCODED */ | |
133 | #define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */ | |
134 | /* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */ | |
135 | ||
136 | /* RCW SRC NOR */ | |
137 | #define RCW_SRC_NOR_VAL (0x20) | |
138 | #define NOR_TYPE_MASK (0x10) | |
139 | #define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */ | |
140 | #define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */ | |
141 | ||
142 | /* RCW SRC Serial Flash | |
143 | * 1. SERIAL NOR (QSPI) | |
144 | * 2. OTHERS (SD/MMC, SPI, I2C1 | |
145 | */ | |
146 | #define RCW_SRC_SERIAL_MASK (0x7F) | |
147 | #define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */ | |
148 | #define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */ | |
149 | #define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */ | |
150 | #define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */ | |
151 | #endif | |
152 | #endif | |
153 | ||
2827d647 SJ |
154 | /* Security Monitor */ |
155 | #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) | |
156 | ||
4a97a0c9 SJ |
157 | /* MMU 500 */ |
158 | #define SMMU_SCR0 (SMMU_BASE + 0x0) | |
159 | #define SMMU_SCR1 (SMMU_BASE + 0x4) | |
160 | #define SMMU_SCR2 (SMMU_BASE + 0x8) | |
161 | #define SMMU_SACR (SMMU_BASE + 0x10) | |
162 | #define SMMU_IDR0 (SMMU_BASE + 0x20) | |
163 | #define SMMU_IDR1 (SMMU_BASE + 0x24) | |
164 | ||
165 | #define SMMU_NSCR0 (SMMU_BASE + 0x400) | |
166 | #define SMMU_NSCR2 (SMMU_BASE + 0x408) | |
167 | #define SMMU_NSACR (SMMU_BASE + 0x410) | |
168 | ||
169 | #define SCR0_CLIENTPD_MASK 0x00000001 | |
170 | #define SCR0_USFCFG_MASK 0x00000400 | |
171 | ||
2827d647 | 172 | |
9f3183d2 MH |
173 | /* PCIe */ |
174 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) | |
175 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) | |
176 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) | |
177 | #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) | |
059d9422 HZ |
178 | #ifdef CONFIG_ARCH_LX2160A |
179 | #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) | |
180 | #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) | |
181 | #endif | |
182 | ||
183 | #ifdef CONFIG_ARCH_LX2160A | |
184 | #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL | |
185 | #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL | |
186 | #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL | |
187 | #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL | |
188 | #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL | |
189 | #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL | |
190 | #elif CONFIG_ARCH_LS1088A | |
c4787f4b HZ |
191 | #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL |
192 | #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL | |
193 | #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL | |
d4ad111d YT |
194 | #elif CONFIG_ARCH_LS1028A |
195 | #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL | |
196 | #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL | |
062d8148 AM |
197 | #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL |
198 | /* this is used by integrated PCI on LS1028, includes ECAM and register space */ | |
199 | #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL | |
c4787f4b | 200 | #else |
9f3183d2 MH |
201 | #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL |
202 | #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL | |
203 | #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL | |
204 | #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL | |
c4787f4b | 205 | #endif |
9f3183d2 MH |
206 | |
207 | /* Device Configuration */ | |
208 | #define DCFG_BASE 0x01e00000 | |
209 | #define DCFG_PORSR1 0x000 | |
210 | #define DCFG_PORSR1_RCW_SRC 0xff800000 | |
211 | #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 | |
212 | #define DCFG_RCWSR13 0x130 | |
213 | #define DCFG_RCWSR13_DSPI (0 << 8) | |
453418f2 YY |
214 | #define DCFG_RCWSR15 0x138 |
215 | #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 | |
9f3183d2 MH |
216 | |
217 | #define DCFG_DCSR_BASE 0X700100000ULL | |
218 | #define DCFG_DCSR_PORCR1 0x000 | |
219 | ||
abc7d0f7 SX |
220 | /* Interrupt Sampling Control */ |
221 | #define ISC_BASE 0x01F70000 | |
222 | #define IRQCR_OFFSET 0x14 | |
223 | ||
9f3183d2 MH |
224 | /* Supplemental Configuration */ |
225 | #define SCFG_BASE 0x01fc0000 | |
226 | #define SCFG_USB3PRM1CR 0x000 | |
ef53b8c4 | 227 | #define SCFG_USB3PRM1CR_INIT 0x27672b2a |
2ab1553f | 228 | #define SCFG_USB_TXVREFTUNE 0x9 |
2a8a3539 | 229 | #define SCFG_USB_SQRXTUNE_MASK 0x7 |
916d9f09 | 230 | #define SCFG_QSPICLKCTLR 0x10 |
9f3183d2 | 231 | |
15d59b53 RW |
232 | #define DCSR_BASE 0x700000000ULL |
233 | #define DCSR_USB_PHY1 0x4600000 | |
234 | #define DCSR_USB_PHY2 0x4610000 | |
235 | #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C | |
236 | #define USB_PHY_RX_EQ_VAL_1 0x0000 | |
237 | #define USB_PHY_RX_EQ_VAL_2 0x0080 | |
238 | #define USB_PHY_RX_EQ_VAL_3 0x0380 | |
239 | #define USB_PHY_RX_EQ_VAL_4 0x0b80 | |
3458a419 RW |
240 | #define DCSR_USB_IOCR1 0x108004 |
241 | #define DCSR_USB_PCSTXSWINGFULL 0x71 | |
15d59b53 | 242 | |
9f3183d2 MH |
243 | #define TP_ITYP_AV 0x00000001 /* Initiator available */ |
244 | #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ | |
245 | #define TP_ITYP_TYPE_ARM 0x0 | |
246 | #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ | |
247 | #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ | |
248 | #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ | |
249 | #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ | |
250 | #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ | |
251 | #define TY_ITYP_VER_A7 0x1 | |
252 | #define TY_ITYP_VER_A53 0x2 | |
253 | #define TY_ITYP_VER_A57 0x3 | |
79119a4d | 254 | #define TY_ITYP_VER_A72 0x4 |
9f3183d2 MH |
255 | |
256 | #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ | |
257 | #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ | |
258 | #define TP_INIT_PER_CLUSTER 4 | |
2f78eae5 | 259 | /* This is chassis generation 3 */ |
f6a70b3a | 260 | #ifndef __ASSEMBLY__ |
2f78eae5 YS |
261 | struct sys_info { |
262 | unsigned long freq_processor[CONFIG_MAX_CPUS]; | |
3564208e | 263 | /* frequency of platform PLL */ |
2f78eae5 YS |
264 | unsigned long freq_systembus; |
265 | unsigned long freq_ddrbus; | |
44937214 | 266 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
b87e6f88 | 267 | unsigned long freq_ddrbus2; |
44937214 | 268 | #endif |
2f78eae5 YS |
269 | unsigned long freq_localbus; |
270 | unsigned long freq_qe; | |
271 | #ifdef CONFIG_SYS_DPAA_FMAN | |
272 | unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; | |
273 | #endif | |
274 | #ifdef CONFIG_SYS_DPAA_QBMAN | |
275 | unsigned long freq_qman; | |
276 | #endif | |
277 | #ifdef CONFIG_SYS_DPAA_PME | |
278 | unsigned long freq_pme; | |
279 | #endif | |
280 | }; | |
281 | ||
282 | /* Global Utilities Block */ | |
283 | struct ccsr_gur { | |
284 | u32 porsr1; /* POR status 1 */ | |
285 | u32 porsr2; /* POR status 2 */ | |
286 | u8 res_008[0x20-0x8]; | |
287 | u32 gpporcr1; /* General-purpose POR configuration */ | |
288 | u32 gpporcr2; /* General-purpose POR configuration 2 */ | |
27f133bb PJ |
289 | u32 gpporcr3; |
290 | u32 gpporcr4; | |
291 | u8 res_030[0x60-0x30]; | |
ed2530d0 | 292 | #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F |
ed2530d0 | 293 | #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F |
23a12cb3 RB |
294 | #if defined(CONFIG_ARCH_LS1088A) |
295 | #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 | |
296 | #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 | |
297 | #else | |
298 | #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 | |
299 | #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 | |
300 | #endif | |
2f78eae5 | 301 | u32 dcfg_fusesr; /* Fuse status register */ |
27f133bb PJ |
302 | u8 res_064[0x70-0x64]; |
303 | u32 devdisr; /* Device disable control 1 */ | |
2f78eae5 YS |
304 | u32 devdisr2; /* Device disable control 2 */ |
305 | u32 devdisr3; /* Device disable control 3 */ | |
306 | u32 devdisr4; /* Device disable control 4 */ | |
307 | u32 devdisr5; /* Device disable control 5 */ | |
308 | u32 devdisr6; /* Device disable control 6 */ | |
27f133bb PJ |
309 | u8 res_088[0x94-0x88]; |
310 | u32 coredisr; /* Device disable control 7 */ | |
9cc2c471 PK |
311 | #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 |
312 | #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 | |
313 | #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 | |
314 | #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 | |
315 | #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 | |
316 | #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 | |
317 | #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 | |
318 | #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 | |
319 | #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 | |
320 | #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 | |
321 | #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 | |
322 | #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 | |
323 | #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 | |
324 | #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 | |
325 | #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 | |
326 | #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 | |
327 | #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 | |
328 | #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 | |
329 | #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 | |
330 | #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 | |
331 | #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 | |
332 | #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 | |
333 | #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 | |
334 | #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 | |
2f78eae5 YS |
335 | u8 res_098[0xa0-0x98]; |
336 | u32 pvr; /* Processor version */ | |
337 | u32 svr; /* System version */ | |
27f133bb PJ |
338 | u8 res_0a8[0x100-0xa8]; |
339 | u32 rcwsr[30]; /* Reset control word status */ | |
2f78eae5 YS |
340 | |
341 | #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 | |
342 | #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f | |
343 | #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 | |
344 | #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f | |
b87e6f88 YS |
345 | #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 |
346 | #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f | |
7b45b383 PK |
347 | |
348 | #if defined(CONFIG_ARCH_LS2080A) | |
31d34c6c ML |
349 | #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 |
350 | #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 | |
351 | #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 | |
352 | #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 | |
7b45b383 PK |
353 | #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK |
354 | #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT | |
355 | #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK | |
356 | #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT | |
357 | #define FSL_CHASSIS3_SRDS1_REGSR 29 | |
358 | #define FSL_CHASSIS3_SRDS2_REGSR 29 | |
4909b89e PJ |
359 | #elif defined(CONFIG_ARCH_LX2160A) |
360 | #define FSL_CHASSIS3_EC1_REGSR 27 | |
361 | #define FSL_CHASSIS3_EC2_REGSR 27 | |
362 | #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 | |
363 | #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 | |
364 | #define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 | |
365 | #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 | |
366 | #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 | |
367 | #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 | |
368 | #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 | |
369 | #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 | |
370 | #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 | |
371 | #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 | |
372 | #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK | |
373 | #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT | |
374 | #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK | |
375 | #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT | |
376 | #define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK | |
377 | #define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT | |
378 | #define FSL_CHASSIS3_SRDS1_REGSR 29 | |
379 | #define FSL_CHASSIS3_SRDS2_REGSR 29 | |
380 | #define FSL_CHASSIS3_SRDS3_REGSR 29 | |
1eba723c PB |
381 | #define FSL_CHASSIS3_RCWSR12_REGSR 12 |
382 | #define FSL_CHASSIS3_RCWSR13_REGSR 13 | |
383 | #define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000 | |
384 | #define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24 | |
385 | #define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038 | |
386 | #define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3 | |
387 | #define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00 | |
388 | #define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9 | |
6d9b82d0 | 389 | #elif defined(CONFIG_ARCH_LS1088A) |
17d066fc AK |
390 | #define FSL_CHASSIS3_EC1_REGSR 26 |
391 | #define FSL_CHASSIS3_EC2_REGSR 26 | |
392 | #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 | |
393 | #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 | |
394 | #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 | |
395 | #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 | |
6d9b82d0 AK |
396 | #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 |
397 | #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 | |
398 | #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF | |
399 | #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0 | |
400 | #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK | |
401 | #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT | |
402 | #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK | |
403 | #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT | |
404 | #define FSL_CHASSIS3_SRDS1_REGSR 29 | |
405 | #define FSL_CHASSIS3_SRDS2_REGSR 30 | |
d4ad111d YT |
406 | #elif defined(CONFIG_ARCH_LS1028A) |
407 | #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 | |
408 | #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 | |
409 | #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK | |
410 | #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT | |
411 | #define FSL_CHASSIS3_SRDS1_REGSR 29 | |
7b45b383 | 412 | #endif |
2827d647 SJ |
413 | #define RCW_SB_EN_REG_INDEX 9 |
414 | #define RCW_SB_EN_MASK 0x00000400 | |
31d34c6c | 415 | |
27f133bb PJ |
416 | u8 res_178[0x200-0x178]; |
417 | u32 scratchrw[16]; /* Scratch Read/Write */ | |
418 | u8 res_240[0x300-0x240]; | |
2f78eae5 YS |
419 | u32 scratchw1r[4]; /* Scratch Read (Write once) */ |
420 | u8 res_310[0x400-0x310]; | |
421 | u32 bootlocptrl; /* Boot location pointer low-order addr */ | |
422 | u32 bootlocptrh; /* Boot location pointer high-order addr */ | |
27f133bb PJ |
423 | u8 res_408[0x520-0x408]; |
424 | u32 usb1_amqr; | |
425 | u32 usb2_amqr; | |
426 | u8 res_528[0x530-0x528]; /* add more registers when needed */ | |
427 | u32 sdmm1_amqr; | |
428 | u8 res_534[0x550-0x534]; /* add more registers when needed */ | |
429 | u32 sata1_amqr; | |
430 | u32 sata2_amqr; | |
431 | u8 res_558[0x570-0x558]; /* add more registers when needed */ | |
432 | u32 misc1_amqr; | |
433 | u8 res_574[0x590-0x574]; /* add more registers when needed */ | |
434 | u32 spare1_amqr; | |
435 | u32 spare2_amqr; | |
436 | u8 res_598[0x620-0x598]; /* add more registers when needed */ | |
437 | u32 gencr[7]; /* General Control Registers */ | |
438 | u8 res_63c[0x640-0x63c]; /* add more registers when needed */ | |
439 | u32 cgensr1; /* Core General Status Register */ | |
440 | u8 res_644[0x660-0x644]; /* add more registers when needed */ | |
441 | u32 cgencr1; /* Core General Control Register */ | |
442 | u8 res_664[0x740-0x664]; /* add more registers when needed */ | |
2f78eae5 YS |
443 | u32 tp_ityp[64]; /* Topology Initiator Type Register */ |
444 | struct { | |
445 | u32 upper; | |
446 | u32 lower; | |
27f133bb PJ |
447 | } tp_cluster[4]; /* Core cluster n Topology Register */ |
448 | u8 res_864[0x920-0x864]; /* add more registers when needed */ | |
449 | u32 ioqoscr[8]; /*I/O Quality of Services Register */ | |
450 | u32 uccr; | |
451 | u8 res_944[0x960-0x944]; /* add more registers when needed */ | |
452 | u32 ftmcr; | |
453 | u8 res_964[0x990-0x964]; /* add more registers when needed */ | |
454 | u32 coredisablesr; | |
455 | u8 res_994[0xa00-0x994]; /* add more registers when needed */ | |
456 | u32 sdbgcr; /*Secure Debug Confifuration Register */ | |
457 | u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */ | |
458 | u32 ipbrr1; | |
459 | u32 ipbrr2; | |
460 | u8 res_858[0x1000-0xc00]; | |
2f78eae5 YS |
461 | }; |
462 | ||
2f78eae5 YS |
463 | struct ccsr_clk_cluster_group { |
464 | struct { | |
465 | u8 res_00[0x10]; | |
466 | u32 csr; | |
467 | u8 res_14[0x20-0x14]; | |
468 | } hwncsr[3]; | |
469 | u8 res_60[0x80-0x60]; | |
470 | struct { | |
471 | u32 gsr; | |
472 | u8 res_84[0xa0-0x84]; | |
473 | } pllngsr[3]; | |
474 | u8 res_e0[0x100-0xe0]; | |
475 | }; | |
476 | ||
477 | struct ccsr_clk_ctrl { | |
478 | struct { | |
479 | u32 csr; /* core cluster n clock control status */ | |
480 | u8 res_04[0x20-0x04]; | |
481 | } clkcncsr[8]; | |
482 | }; | |
40f8dec5 YS |
483 | |
484 | struct ccsr_reset { | |
485 | u32 rstcr; /* 0x000 */ | |
486 | u32 rstcrsp; /* 0x004 */ | |
487 | u8 res_008[0x10-0x08]; /* 0x008 */ | |
488 | u32 rstrqmr1; /* 0x010 */ | |
489 | u32 rstrqmr2; /* 0x014 */ | |
490 | u32 rstrqsr1; /* 0x018 */ | |
491 | u32 rstrqsr2; /* 0x01c */ | |
492 | u32 rstrqwdtmrl; /* 0x020 */ | |
493 | u32 rstrqwdtmru; /* 0x024 */ | |
494 | u8 res_028[0x30-0x28]; /* 0x028 */ | |
495 | u32 rstrqwdtsrl; /* 0x030 */ | |
496 | u32 rstrqwdtsru; /* 0x034 */ | |
497 | u8 res_038[0x60-0x38]; /* 0x038 */ | |
498 | u32 brrl; /* 0x060 */ | |
499 | u32 brru; /* 0x064 */ | |
500 | u8 res_068[0x80-0x68]; /* 0x068 */ | |
501 | u32 pirset; /* 0x080 */ | |
502 | u32 pirclr; /* 0x084 */ | |
503 | u8 res_088[0x90-0x88]; /* 0x088 */ | |
504 | u32 brcorenbr; /* 0x090 */ | |
505 | u8 res_094[0x100-0x94]; /* 0x094 */ | |
506 | u32 rcw_reqr; /* 0x100 */ | |
507 | u32 rcw_completion; /* 0x104 */ | |
508 | u8 res_108[0x110-0x108]; /* 0x108 */ | |
509 | u32 pbi_reqr; /* 0x110 */ | |
510 | u32 pbi_completion; /* 0x114 */ | |
511 | u8 res_118[0xa00-0x118]; /* 0x118 */ | |
512 | u32 qmbm_warmrst; /* 0xa00 */ | |
513 | u32 soc_warmrst; /* 0xa04 */ | |
514 | u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ | |
515 | u32 ip_rev1; /* 0xbf8 */ | |
516 | u32 ip_rev2; /* 0xbfc */ | |
517 | }; | |
6fb522dc | 518 | |
a1f95ff7 RB |
519 | struct ccsr_serdes { |
520 | struct { | |
521 | u32 rstctl; /* Reset Control Register */ | |
522 | u32 pllcr0; /* PLL Control Register 0 */ | |
523 | u32 pllcr1; /* PLL Control Register 1 */ | |
524 | u32 pllcr2; /* PLL Control Register 2 */ | |
525 | u32 pllcr3; /* PLL Control Register 3 */ | |
526 | u32 pllcr4; /* PLL Control Register 4 */ | |
527 | u32 pllcr5; /* PLL Control Register 5 */ | |
528 | u8 res[0x20 - 0x1c]; | |
529 | } bank[2]; | |
530 | u8 res1[0x90 - 0x40]; | |
531 | u32 srdstcalcr; /* TX Calibration Control */ | |
532 | u32 srdstcalcr1; /* TX Calibration Control1 */ | |
533 | u8 res2[0xa0 - 0x98]; | |
534 | u32 srdsrcalcr; /* RX Calibration Control */ | |
535 | u32 srdsrcalcr1; /* RX Calibration Control1 */ | |
536 | u8 res3[0xb0 - 0xa8]; | |
537 | u32 srdsgr0; /* General Register 0 */ | |
538 | u8 res4[0x800 - 0xb4]; | |
539 | struct serdes_lane { | |
540 | u32 gcr0; /* General Control Register 0 */ | |
541 | u32 gcr1; /* General Control Register 1 */ | |
542 | u32 gcr2; /* General Control Register 2 */ | |
543 | u32 ssc0; /* Speed Switch Control 0 */ | |
544 | u32 rec0; /* Receive Equalization Control 0 */ | |
545 | u32 rec1; /* Receive Equalization Control 1 */ | |
546 | u32 tec0; /* Transmit Equalization Control 0 */ | |
547 | u32 ssc1; /* Speed Switch Control 1 */ | |
548 | u8 res1[0x840 - 0x820]; | |
549 | } lane[8]; | |
550 | u8 res5[0x19fc - 0xa00]; | |
551 | }; | |
552 | ||
f6a70b3a | 553 | #endif /*__ASSEMBLY__*/ |
9f3183d2 | 554 | #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ |