[thirdparty/u-boot.git] / arch / arm / mach-omap2 / am33xx / clock_am43xx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * clock_am43xx.c
 *
 * clocks for AM43XX based boards
 * Derived from AM33XX based boards
 *
 * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
 */

#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>

struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;

const struct dpll_regs dpll_mpu_regs = {
	.cm_clkmode_dpll	= CM_WKUP + 0x560,
	.cm_idlest_dpll		= CM_WKUP + 0x564,
	.cm_clksel_dpll		= CM_WKUP + 0x56c,
	.cm_div_m2_dpll		= CM_WKUP + 0x570,
};

const struct dpll_regs dpll_core_regs = {
	.cm_clkmode_dpll	= CM_WKUP + 0x520,
	.cm_idlest_dpll		= CM_WKUP + 0x524,
	.cm_clksel_dpll		= CM_WKUP + 0x52C,
	.cm_div_m4_dpll		= CM_WKUP + 0x538,
	.cm_div_m5_dpll		= CM_WKUP + 0x53C,
	.cm_div_m6_dpll		= CM_WKUP + 0x540,
};

const struct dpll_regs dpll_per_regs = {
	.cm_clkmode_dpll	= CM_WKUP + 0x5E0,
	.cm_idlest_dpll		= CM_WKUP + 0x5E4,
	.cm_clksel_dpll		= CM_WKUP + 0x5EC,
	.cm_div_m2_dpll		= CM_WKUP + 0x5F0,
};

const struct dpll_regs dpll_ddr_regs = {
	.cm_clkmode_dpll	= CM_WKUP + 0x5A0,
	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
	.cm_div_m4_dpll		= CM_WKUP + 0x5B8,
};

void setup_clocks_for_console(void)
{
	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;

	/* Do not add any spl_debug prints in this function */
	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
			CD_CLKCTRL_CLKTRCTRL_SHIFT);

	/* Enable UART0 */
	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
			MODULE_CLKCTRL_MODULEMODE_MASK,
			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
			MODULE_CLKCTRL_MODULEMODE_SHIFT);

	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
		clkctrl = readl(&cmwkup->wkup_uart0ctrl);
		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
			 MODULE_CLKCTRL_IDLEST_SHIFT;
	}
}

void enable_basic_clocks(void)
{
	u32 *const clk_domains[] = {
		&cmper->l3clkstctrl,
		&cmper->l3sclkstctrl,
		&cmper->l4lsclkstctrl,
		&cmwkup->wkclkstctrl,
		&cmper->emifclkstctrl,
		0
	};

	u32 *const clk_modules_explicit_en[] = {
		&cmper->l3clkctrl,
		&cmper->l4lsclkctrl,
		&cmper->l4fwclkctrl,
		&cmwkup->wkl4wkclkctrl,
		&cmper->l3instrclkctrl,
		&cmper->l4hsclkctrl,
		&cmwkup->wkgpio0clkctrl,
		&cmwkup->wkctrlclkctrl,
		&cmper->timer2clkctrl,
		&cmper->gpmcclkctrl,
		&cmper->elmclkctrl,
		&cmper->mmc0clkctrl,
		&cmper->mmc1clkctrl,
		&cmwkup->wkup_i2c0ctrl,
		&cmper->gpio1clkctrl,
		&cmper->gpio2clkctrl,
		&cmper->gpio3clkctrl,
		&cmper->gpio4clkctrl,
		&cmper->gpio5clkctrl,
		&cmper->i2c1clkctrl,
		&cmper->cpgmac0clkctrl,
		&cmper->emiffwclkctrl,
		&cmper->emifclkctrl,
		&cmper->otfaemifclkctrl,
		&cmper->qspiclkctrl,
		&cmper->spi0clkctrl,
		0
	};

	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);

	/* Select the Master osc clk as Timer2 clock source */
	writel(0x1, &cmdpll->clktimer2clk);

	/* For OPP100 the mac clock should be /5. */
	writel(0x4, &cmdpll->clkselmacclk);
}

void rtc_only_enable_basic_clocks(void)
{
	u32 *const clk_domains[] = {
		&cmper->emifclkstctrl,
		0
	};

	u32 *const clk_modules_explicit_en[] = {
		&cmper->gpio5clkctrl,
		&cmper->emiffwclkctrl,
		&cmper->emifclkctrl,
		&cmper->otfaemifclkctrl,
		0
	};

	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);

	/* Select the Master osc clk as Timer2 clock source */
	writel(0x1, &cmdpll->clktimer2clk);
}

#ifdef CONFIG_TI_EDMA3
void enable_edma3_clocks(void)
{
	u32 *const clk_domains_edma3[] = {
		0
	};

	u32 *const clk_modules_explicit_en_edma3[] = {
		&cmper->tpccclkctrl,
		&cmper->tptc0clkctrl,
		0
	};

	do_enable_clocks(clk_domains_edma3,
			 clk_modules_explicit_en_edma3,
			 1);
}

void disable_edma3_clocks(void)
{
	u32 *const clk_domains_edma3[] = {
		0
	};

	u32 *const clk_modules_disable_edma3[] = {
		&cmper->tpccclkctrl,
		&cmper->tptc0clkctrl,
		0
	};

	do_disable_clocks(clk_domains_edma3,
			  clk_modules_disable_edma3,
			  1);
}
#endif

#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
	u32 *usbclkctrl = 0;
	u32 *usbphyocp2scpclkctrl = 0;

	if (index == 0) {
		usbclkctrl = &cmper->usb0clkctrl;
		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
		setbits_le32(&cmper->usb0clkctrl,
			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
		setbits_le32(&cmwkup->usbphy0clkctrl,
			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	} else if (index == 1) {
		usbclkctrl = &cmper->usb1clkctrl;
		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
		setbits_le32(&cmper->usb1clkctrl,
			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
		setbits_le32(&cmwkup->usbphy1clkctrl,
			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	}

	u32 *const clk_domains_usb[] = {
		0
	};

	u32 *const clk_modules_explicit_en_usb[] = {
		usbclkctrl,
		usbphyocp2scpclkctrl,
		0
	};

	do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
}

void disable_usb_clocks(int index)
{
	u32 *usbclkctrl = 0;
	u32 *usbphyocp2scpclkctrl = 0;

	if (index == 0) {
		usbclkctrl = &cmper->usb0clkctrl;
		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
		clrbits_le32(&cmper->usb0clkctrl,
			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
		clrbits_le32(&cmwkup->usbphy0clkctrl,
			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	} else if (index == 1) {
		usbclkctrl = &cmper->usb1clkctrl;
		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
		clrbits_le32(&cmper->usb1clkctrl,
			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
		clrbits_le32(&cmwkup->usbphy1clkctrl,
			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	}

	u32 *const clk_domains_usb[] = {
		0
	};

	u32 *const clk_modules_disable_usb[] = {
		usbclkctrl,
		usbphyocp2scpclkctrl,
		0
	};

	do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3b34ac13 LV	2	/*
	3	* clock_am43xx.c
	4	*
	5	* clocks for AM43XX based boards
	6	* Derived from AM33XX based boards
	7	*
a94a4071	8	* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
3b34ac13 LV	9	*/
	10
	11	#include <common.h>
	12	#include <asm/arch/cpu.h>
	13	#include <asm/arch/clock.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/io.h>
	17
	18	struct cm_perpll const cmper = (struct cm_perpll )CM_PER;
	19	struct cm_wkuppll const cmwkup = (struct cm_wkuppll )CM_WKUP;
0d54cb92	20	struct cm_dpll const cmdpll = (struct cm_dpll )CM_DPLL;
3b34ac13 LV	21
	22	const struct dpll_regs dpll_mpu_regs = {
	23	.cm_clkmode_dpll = CM_WKUP + 0x560,
	24	.cm_idlest_dpll = CM_WKUP + 0x564,
	25	.cm_clksel_dpll = CM_WKUP + 0x56c,
	26	.cm_div_m2_dpll = CM_WKUP + 0x570,
	27	};
	28
	29	const struct dpll_regs dpll_core_regs = {
	30	.cm_clkmode_dpll = CM_WKUP + 0x520,
	31	.cm_idlest_dpll = CM_WKUP + 0x524,
	32	.cm_clksel_dpll = CM_WKUP + 0x52C,
	33	.cm_div_m4_dpll = CM_WKUP + 0x538,
	34	.cm_div_m5_dpll = CM_WKUP + 0x53C,
	35	.cm_div_m6_dpll = CM_WKUP + 0x540,
	36	};
	37
	38	const struct dpll_regs dpll_per_regs = {
	39	.cm_clkmode_dpll = CM_WKUP + 0x5E0,
	40	.cm_idlest_dpll = CM_WKUP + 0x5E4,
	41	.cm_clksel_dpll = CM_WKUP + 0x5EC,
	42	.cm_div_m2_dpll = CM_WKUP + 0x5F0,
	43	};
	44
	45	const struct dpll_regs dpll_ddr_regs = {
	46	.cm_clkmode_dpll = CM_WKUP + 0x5A0,
	47	.cm_idlest_dpll = CM_WKUP + 0x5A4,
	48	.cm_clksel_dpll = CM_WKUP + 0x5AC,
	49	.cm_div_m2_dpll = CM_WKUP + 0x5B0,
cf04d032	50	.cm_div_m4_dpll = CM_WKUP + 0x5B8,
3b34ac13 LV	51	};
3b34ac13 LV	52
3b34ac13 LV	53	void setup_clocks_for_console(void)
3b34ac13 LV	54	{
ccd2f8db LV	55	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
ccd2f8db LV	56
3b34ac13 LV	57	/* Do not add any spl_debug prints in this function */
	58	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
	59	CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
	60	CD_CLKCTRL_CLKTRCTRL_SHIFT);
	61
	62	/* Enable UART0 */
	63	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
	64	MODULE_CLKCTRL_MODULEMODE_MASK,
	65	MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
	66	MODULE_CLKCTRL_MODULEMODE_SHIFT);
ccd2f8db LV	67
	68	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) \|\|
	69	(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
	70	clkctrl = readl(&cmwkup->wkup_uart0ctrl);
	71	idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
	72	MODULE_CLKCTRL_IDLEST_SHIFT;
	73	}
3b34ac13 LV	74	}
	75
	76	void enable_basic_clocks(void)
	77	{
	78	u32 *const clk_domains[] = {
	79	&cmper->l3clkstctrl,
	80	&cmper->l3sclkstctrl,
	81	&cmper->l4lsclkstctrl,
	82	&cmwkup->wkclkstctrl,
	83	&cmper->emifclkstctrl,
	84	0
	85	};
	86
	87	u32 *const clk_modules_explicit_en[] = {
	88	&cmper->l3clkctrl,
	89	&cmper->l4lsclkctrl,
	90	&cmper->l4fwclkctrl,
	91	&cmwkup->wkl4wkclkctrl,
	92	&cmper->l3instrclkctrl,
	93	&cmper->l4hsclkctrl,
	94	&cmwkup->wkgpio0clkctrl,
	95	&cmwkup->wkctrlclkctrl,
	96	&cmper->timer2clkctrl,
	97	&cmper->gpmcclkctrl,
	98	&cmper->elmclkctrl,
	99	&cmper->mmc0clkctrl,
	100	&cmper->mmc1clkctrl,
	101	&cmwkup->wkup_i2c0ctrl,
	102	&cmper->gpio1clkctrl,
	103	&cmper->gpio2clkctrl,
	104	&cmper->gpio3clkctrl,
cd8341b7 DG	105	&cmper->gpio4clkctrl,
cd8341b7 DG	106	&cmper->gpio5clkctrl,
3b34ac13	107	&cmper->i2c1clkctrl,
2cab8ae8	108	&cmper->cpgmac0clkctrl,
3b34ac13 LV	109	&cmper->emiffwclkctrl,
	110	&cmper->emifclkctrl,
	111	&cmper->otfaemifclkctrl,
b56e71e2	112	&cmper->qspiclkctrl,
6ff31a7f	113	&cmper->spi0clkctrl,
3b34ac13 LV	114	0
	115	};
	116
	117	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
0d54cb92 LV	118
	119	/* Select the Master osc clk as Timer2 clock source */
	120	writel(0x1, &cmdpll->clktimer2clk);
bba379d4 SK	121
	122	/* For OPP100 the mac clock should be /5. */
	123	writel(0x4, &cmdpll->clkselmacclk);
3b34ac13	124	}
5b3b0d68	125
7619badb TK	126	void rtc_only_enable_basic_clocks(void)
	127	{
	128	u32 *const clk_domains[] = {
	129	&cmper->emifclkstctrl,
	130	0
	131	};
	132
	133	u32 *const clk_modules_explicit_en[] = {
	134	&cmper->gpio5clkctrl,
	135	&cmper->emiffwclkctrl,
	136	&cmper->emifclkctrl,
	137	&cmper->otfaemifclkctrl,
	138	0
	139	};
	140
	141	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
	142
	143	/* Select the Master osc clk as Timer2 clock source */
	144	writel(0x1, &cmdpll->clktimer2clk);
	145	}
	146
5b3b0d68 V	147	#ifdef CONFIG_TI_EDMA3
	148	void enable_edma3_clocks(void)
	149	{
	150	u32 *const clk_domains_edma3[] = {
	151	0
	152	};
	153
	154	u32 *const clk_modules_explicit_en_edma3[] = {
	155	&cmper->tpccclkctrl,
	156	&cmper->tptc0clkctrl,
	157	0
	158	};
	159
	160	do_enable_clocks(clk_domains_edma3,
	161	clk_modules_explicit_en_edma3,
	162	1);
	163	}
	164
	165	void disable_edma3_clocks(void)
	166	{
	167	u32 *const clk_domains_edma3[] = {
	168	0
	169	};
	170
	171	u32 *const clk_modules_disable_edma3[] = {
	172	&cmper->tpccclkctrl,
	173	&cmper->tptc0clkctrl,
	174	0
	175	};
	176
	177	do_disable_clocks(clk_domains_edma3,
	178	clk_modules_disable_edma3,
	179	1);
	180	}
	181	#endif
09cc14f4	182
383f4a0e	183	#if defined(CONFIG_USB_DWC3) \|\| defined(CONFIG_USB_XHCI_OMAP)
09cc14f4 KVA	184	void enable_usb_clocks(int index)
	185	{
	186	u32 *usbclkctrl = 0;
	187	u32 *usbphyocp2scpclkctrl = 0;
	188
	189	if (index == 0) {
	190	usbclkctrl = &cmper->usb0clkctrl;
	191	usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
	192	setbits_le32(&cmper->usb0clkctrl,
	193	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
	194	setbits_le32(&cmwkup->usbphy0clkctrl,
	195	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	196	} else if (index == 1) {
	197	usbclkctrl = &cmper->usb1clkctrl;
	198	usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
	199	setbits_le32(&cmper->usb1clkctrl,
	200	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
	201	setbits_le32(&cmwkup->usbphy1clkctrl,
	202	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	203	}
	204
	205	u32 *const clk_domains_usb[] = {
	206	0
	207	};
	208
	209	u32 *const clk_modules_explicit_en_usb[] = {
	210	usbclkctrl,
	211	usbphyocp2scpclkctrl,
	212	0
	213	};
	214
	215	do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
	216	}
	217
	218	void disable_usb_clocks(int index)
	219	{
	220	u32 *usbclkctrl = 0;
	221	u32 *usbphyocp2scpclkctrl = 0;
	222
	223	if (index == 0) {
	224	usbclkctrl = &cmper->usb0clkctrl;
	225	usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
	226	clrbits_le32(&cmper->usb0clkctrl,
	227	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
	228	clrbits_le32(&cmwkup->usbphy0clkctrl,
	229	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	230	} else if (index == 1) {
	231	usbclkctrl = &cmper->usb1clkctrl;
	232	usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
	233	clrbits_le32(&cmper->usb1clkctrl,
	234	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
	235	clrbits_le32(&cmwkup->usbphy1clkctrl,
	236	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
	237	}
	238
	239	u32 *const clk_domains_usb[] = {
	240	0
	241	};
	242
	243	u32 *const clk_modules_disable_usb[] = {
	244	usbclkctrl,
	245	usbphyocp2scpclkctrl,
	246	0
	247	};
248
249	do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
250	}
251	#endif