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1e52fea3 ML |
1 | /* |
2 | * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c | |
3 | * | |
4 | * Generate definitions needed by assembly language modules. | |
5 | * This code generates raw asm output which is post-processed to extract | |
6 | * and format the required data. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <common.h> | |
13 | ||
14 | #include <linux/kbuild.h> | |
15 | ||
16 | int main(void) | |
17 | { | |
254d68b6 MY |
18 | /* |
19 | * TODO : Check if each entry in this file is really necessary. | |
20 | * - struct ftahbc02s | |
21 | * - struct ftsdmc021 | |
22 | * - struct andes_pcu | |
23 | * - struct dwcddr21mctl | |
24 | * are used only for generating asm-offsets.h. | |
25 | * It means their offset addresses are referenced only from assembly | |
26 | * code. Is it better to define the macros directly in headers? | |
27 | */ | |
28 | ||
1e52fea3 ML |
29 | #ifdef CONFIG_FTSMC020 |
30 | OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); | |
31 | OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); | |
32 | #endif | |
33 | BLANK(); | |
34 | #ifdef CONFIG_FTAHBC020S | |
254d68b6 | 35 | OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); |
1e52fea3 ML |
36 | OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); |
37 | OFFSET(FTAHBC020S_CR, ftahbc02s, cr); | |
38 | #endif | |
39 | BLANK(); | |
254d68b6 MY |
40 | #ifdef CONFIG_FTPMU010 |
41 | OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); | |
42 | #endif | |
43 | BLANK(); | |
44 | #ifdef CONFIG_FTSDMC021 | |
45 | OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); | |
46 | OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); | |
47 | OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); | |
48 | OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); | |
49 | OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); | |
50 | OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); | |
51 | OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); | |
52 | OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); | |
53 | #endif | |
54 | BLANK(); | |
1e52fea3 ML |
55 | #ifdef CONFIG_ANDES_PCU |
56 | OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ | |
57 | #endif | |
58 | BLANK(); | |
59 | #ifdef CONFIG_DWCDDR21MCTL | |
60 | OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */ | |
61 | OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ | |
62 | OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */ | |
63 | OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */ | |
64 | OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */ | |
65 | OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */ | |
66 | OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */ | |
67 | OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */ | |
68 | OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */ | |
69 | OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */ | |
70 | OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */ | |
71 | OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */ | |
72 | OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */ | |
73 | OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */ | |
74 | OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */ | |
75 | OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */ | |
76 | OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */ | |
77 | OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ | |
78 | OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ | |
79 | #endif | |
254d68b6 | 80 | |
1e52fea3 ML |
81 | return 0; |
82 | } |