[thirdparty/u-boot.git] / board / freescale / c29xpcie / README

Overview
=========
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.
It includes C293PCIE board, C293PCIE board and C291PCIE board.
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engines.
(maximum core frequency 1000/1200 MHz).

The C29xPCIE board features are as follows:
Memory subsystem:
	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	- 64 Mbyte NOR flash single-chip memory
	- 4 Gbyte NAND flash memory
	- 1 Mbit AT24C1024 I2C EEPROM
	- 16 Mbyte SPI memory

Interfaces:
	- 10/100/1000 BaseT Ethernet ports:
		- eTSEC1, RGMII: one 10/100/1000 port
		- eTSEC2, RGMII: one 10/100/1000 port
	- DUART interface:
		- DUART interface: supports two UARTs up to 115200 bps for
		   console display

Board connectors:
	- Mini-ITX power supply connector
	- JTAG/COP for debugging

Physical Memory Map on C29xPCIE
===============================
Address Start   Address End   Memory type
0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR

Serial Port Configuration on C29xPCIE
=====================================
Configure the serial port of the attached computer with the following values:
	-Data rate: 115200 bps
	-Number of data bits: 8
	-Parity: None
	-Number of Stop bits: 1
	-Flow Control: Hardware/None

Settings of DIP-switch
======================
  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
Note: 1 stands for 'off', 0 stands for 'on'

Build and program U-Boot to NOR flash
==================================
1. Build u-boot.bin image example:
	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	make C293PCIE

2. Program u-boot.bin into NOR flash
	=> tftp $loadaddr $uboot
	=> protect off eff40000 +$filesize
	=> erase eff40000 +$filesize
	=> cp.b $loadaddr eff40000 $filesize

3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.

Alternate NOR bank
==================
There are four banks in C29XPCIE board, example to change bank booting:
1. Program u-boot.bin into alternate NOR bank
	=> tftp $loadaddr $uboot
	=> protect off e9f40000 +$filesize
	=> erase e9f40000 +$filesize
	=> cp.b $loadaddr e9f40000 $filesize

2. Switch to alternate NOR bank
	=> cpld_cmd reset altbank [bank]
	- [bank] bank value select 1-4
	- bank 1 on the flash 0x0000000~0x0ffffff
	- bank 2 on the flash 0x1000000~0x1ffffff
	- bank 3 on the flash 0x2000000~0x2ffffff
	- bank 4 on the flash 0x3000000~0x3ffffff
	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.

Build and program U-Boot to SPI flash
==================================
1. Build u-boot-spi.bin image
	make C29xPCIE_SPIFLASH_config; make
	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.

2. Program u-boot-spi.bin into SPI flash
	=> tftp $loadaddr $uboot-spi
	=> sf erase 0 100000
	=> sf write $loadaddr 0 $filesize

3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
Commit	Line	Data
28103120 PL	1	Overview
	2	=========
	3	C29XPCIE board is a series of Freescale PCIe add-in cards to perform
	4	as public key crypto accelerator or secure key management module.
	5	It includes C293PCIE board, C293PCIE board and C291PCIE board.
	6	The Freescale C29x family is a high performance crypto co-processor.
	7	It combines a single e500v2 core with necessary SEC engines.
	8	(maximum core frequency 1000/1200 MHz).
	9
	10	The C29xPCIE board features are as follows:
	11	Memory subsystem:
	12	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	13	- 64 Mbyte NOR flash single-chip memory
	14	- 4 Gbyte NAND flash memory
	15	- 1 Mbit AT24C1024 I2C EEPROM
	16	- 16 Mbyte SPI memory
	17
	18	Interfaces:
	19	- 10/100/1000 BaseT Ethernet ports:
	20	- eTSEC1, RGMII: one 10/100/1000 port
	21	- eTSEC2, RGMII: one 10/100/1000 port
	22	- DUART interface:
	23	- DUART interface: supports two UARTs up to 115200 bps for
	24	console display
	25
	26	Board connectors:
	27	- Mini-ITX power supply connector
	28	- JTAG/COP for debugging
	29
	30	Physical Memory Map on C29xPCIE
	31	===============================
	32	Address Start Address End Memory type
	33	0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
	34	0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
	35	0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
	36	0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
	37	0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
	38	0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
	39	0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
	40
	41	Serial Port Configuration on C29xPCIE
	42	=====================================
	43	Configure the serial port of the attached computer with the following values:
	44	-Data rate: 115200 bps
	45	-Number of data bits: 8
	46	-Parity: None
	47	-Number of Stop bits: 1
	48	-Flow Control: Hardware/None
	49
	50	Settings of DIP-switch
	51	======================
	52	SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
	53	SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
	54	Note: 1 stands for 'off', 0 stands for 'on'
	55
a187559e	56	Build and program U-Boot to NOR flash
28103120 PL	57	==================================
28103120 PL	58	1. Build u-boot.bin image example:
28103120 PL	59	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	60	make C293PCIE
	61
	62	2. Program u-boot.bin into NOR flash
	63	=> tftp $loadaddr $uboot
e222b1f3 PK	64	=> protect off eff40000 +$filesize
	65	=> erase eff40000 +$filesize
	66	=> cp.b $loadaddr eff40000 $filesize
28103120 PL	67
	68	3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
	69
	70	Alternate NOR bank
	71	==================
	72	There are four banks in C29XPCIE board, example to change bank booting:
	73	1. Program u-boot.bin into alternate NOR bank
	74	=> tftp $loadaddr $uboot
e222b1f3 PK	75	=> protect off e9f40000 +$filesize
	76	=> erase e9f40000 +$filesize
	77	=> cp.b $loadaddr e9f40000 $filesize
28103120 PL	78
	79	2. Switch to alternate NOR bank
	80	=> cpld_cmd reset altbank [bank]
	81	- [bank] bank value select 1-4
	82	- bank 1 on the flash 0x0000000~0x0ffffff
	83	- bank 2 on the flash 0x1000000~0x1ffffff
	84	- bank 3 on the flash 0x2000000~0x2ffffff
	85	- bank 4 on the flash 0x3000000~0x3ffffff
	86	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
	87
a187559e	88	Build and program U-Boot to SPI flash
28103120 PL	89	==================================
	90	1. Build u-boot-spi.bin image
	91	make C29xPCIE_SPIFLASH_config; make
	92	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
	93
	94	2. Program u-boot-spi.bin into SPI flash
	95	=> tftp $loadaddr $uboot-spi
	96	=> sf erase 0 100000
	97	=> sf write $loadaddr 0 $filesize
	98
	99	3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.