[thirdparty/u-boot.git] / board / sbc8548 / sbc8548.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
 *
 * Copyright 2007 Embedded Specialties, Inc.
 *
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>

void local_bus_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;

	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
			in_8(rev) >> 4);

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);

	lbc_mhz = sysinfo.freq_localbus / 1000000;
	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;

	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16) {
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	} else if (clkdiv == 8) {
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	} else if (clkdiv == 4) {
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	}

	/*
	 * Local Bus Clock > 83.3 MHz. According to timing
	 * specifications set LCRR[EADC] to 2 delay cycles.
	 */
	if (lbc_mhz > 83) {
		lcrr &= ~LCRR_EADC;
		lcrr |= LCRR_EADC_2;
	}

	/*
	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	 * disable PLL bypass for Local Bus Clock > 83 MHz.
	 */
	if (lbc_mhz >= 66)
		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */

	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32(&lbc->lcrr, lcrr);
	asm("sync;isync;msync");

	 /*
	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
	 * and terminate with isync
	 */
	lcrr = in_be32(&lbc->lcrr);
	asm ("isync;");

	/* let DLL stabilize */
	udelay(500);

	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)

	uint idx;
	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);

	puts("    SDRAM: ");

	print_size(size, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);

	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
	asm("msync");

	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
	asm("msync");

	/*
	 * Issue PRECHARGE ALL command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		*sdram_addr2 = 0xff;
		ppcDcbf((unsigned long) sdram_addr2);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue RFEN command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif	/* CONFIG_PCI1 */

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int first_free_busno = 0;

#ifdef CONFIG_PCI1
	struct fsl_pci_info pci_info;
	u32 devdisr = in_be32(&gur->devdisr);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 porpllsr = in_be32(&gur->porpllsr);

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */

		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33000000) ? "33" :
			(pci_speed == 66000000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_arb ? "arbiter" : "external-arbiter");

		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */

	fsl_pcie_init_board(first_free_busno);
}
#endif

int board_eth_init(bd_t *bis)
{
	tsec_standard_init(bis);
	pci_eth_init(bis);
	return 0;	/* otherwise cpu_eth_init gets run */
}

int last_stage_init(void)
{
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_FSL_PCI_INIT
	FT_FSL_PCI_SETUP;
#endif

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
11c45ebd	2	/*
bd42bbb8 PG	3	* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
bd42bbb8 PG	4	*
11c45ebd JH	5	* Copyright 2007 Embedded Specialties, Inc.
	6	*
	7	* Copyright 2004, 2007 Freescale Semiconductor.
	8	*
	9	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11c45ebd JH	10	*/
	11
	12	#include <common.h>
2cf431c2	13	#include <init.h>
90526e9f	14	#include <net.h>
11c45ebd JH	15	#include <pci.h>
	16	#include <asm/processor.h>
	17	#include <asm/immap_85xx.h>
c8514622	18	#include <asm/fsl_pci.h>
5614e71b	19	#include <fsl_ddr_sdram.h>
5d27e02c	20	#include <asm/fsl_serdes.h>
a30a549a	21	#include <spd_sdram.h>
94ca0914 PG	22	#include <netdev.h>
94ca0914 PG	23	#include <tsec.h>
11c45ebd	24	#include <miiphy.h>
b08c8c48	25	#include <linux/libfdt.h>
11c45ebd JH	26	#include <fdt_support.h>
11c45ebd JH	27
11c45ebd	28	void local_bus_init(void);
11c45ebd JH	29
	30	int board_early_init_f (void)
	31	{
	32	return 0;
	33	}
	34
	35	int checkboard (void)
	36	{
6d0f6bcf JCPV	37	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6d0f6bcf JCPV	38	volatile u_char rev= (void )CONFIG_SYS_BD_REV;
11c45ebd JH	39
11c45ebd JH	40	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
0c7e4d45	41	in_8(rev) >> 4);
11c45ebd JH	42
	43	/*
	44	* Initialize local bus.
	45	*/
	46	local_bus_init ();
	47
0c7e4d45 PG	48	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
0c7e4d45 PG	49	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
11c45ebd JH	50	return 0;
	51	}
	52
11c45ebd JH	53	/*
	54	* Initialize Local Bus
	55	*/
	56	void
	57	local_bus_init(void)
	58	{
6d0f6bcf	59	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	60	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
11c45ebd	61
e2b363ff	62	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
11c45ebd JH	63	sys_info_t sysinfo;
	64
	65	get_sys_info(&sysinfo);
e2b363ff	66
997399fa PK	67	lbc_mhz = sysinfo.freq_localbus / 1000000;
997399fa PK	68	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
e2b363ff PG	69
e2b363ff PG	70	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
11c45ebd	71
0c7e4d45	72	out_be32(&gur->lbiuiplldcr1, 0x00078080);
11c45ebd	73	if (clkdiv == 16) {
0c7e4d45	74	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
11c45ebd	75	} else if (clkdiv == 8) {
0c7e4d45	76	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
11c45ebd	77	} else if (clkdiv == 4) {
0c7e4d45	78	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
11c45ebd JH	79	}
11c45ebd JH	80
e2b363ff PG	81	/*
	82	* Local Bus Clock > 83.3 MHz. According to timing
	83	* specifications set LCRR[EADC] to 2 delay cycles.
	84	*/
	85	if (lbc_mhz > 83) {
	86	lcrr &= ~LCRR_EADC;
	87	lcrr \|= LCRR_EADC_2;
	88	}
	89
	90	/*
	91	* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	92	* disable PLL bypass for Local Bus Clock > 83 MHz.
	93	*/
	94	if (lbc_mhz >= 66)
	95	lcrr &= (~LCRR_DBYP); /* DLL Enabled */
	96
	97	else
	98	lcrr \|= LCRR_DBYP; /* DLL Bypass */
11c45ebd	99
e2b363ff	100	out_be32(&lbc->lcrr, lcrr);
11c45ebd JH	101	asm("sync;isync;msync");
11c45ebd JH	102
e2b363ff PG	103	/*
	104	* According to MPC8548ERMAD Rev.1.3 read back LCRR
	105	* and terminate with isync
	106	*/
	107	lcrr = in_be32(&lbc->lcrr);
	108	asm ("isync;");
	109
	110	/* let DLL stabilize */
	111	udelay(500);
	112
0c7e4d45 PG	113	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
0c7e4d45 PG	114	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
11c45ebd JH	115	}
	116
	117	/*
	118	* Initialize SDRAM memory on the Local Bus.
	119	*/
70961ba4	120	void lbc_sdram_init(void)
11c45ebd	121	{
11d5a629	122	#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
11c45ebd JH	123
11c45ebd JH	124	uint idx;
5f4c6f0d	125	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
f51cdaf1	126	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	127	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
5f4c6f0d	128	uint sdram_addr2 = (uint )(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
11c45ebd JH	129
	130	puts(" SDRAM: ");
	131
5f4c6f0d	132	print_size(size, "\n");
11c45ebd JH	133
	134	/*
	135	* Setup SDRAM Base and Option Registers
	136	*/
f51cdaf1 BB	137	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	138	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	139	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	140	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
11d5a629	141
0c7e4d45	142	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
11c45ebd JH	143	asm("msync");
11c45ebd JH	144
0c7e4d45 PG	145	out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
0c7e4d45 PG	146	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
11c45ebd JH	147	asm("msync");
11c45ebd JH	148
11c45ebd JH	149	/*
	150	* Issue PRECHARGE ALL command.
	151	*/
5f4c6f0d	152	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
11c45ebd JH	153	asm("sync;msync");
	154	*sdram_addr = 0xff;
	155	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	156	*sdram_addr2 = 0xff;
5f4c6f0d PG	157	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	158	udelay(100);
	159
	160	/*
	161	* Issue 8 AUTO REFRESH commands.
	162	*/
	163	for (idx = 0; idx < 8; idx++) {
5f4c6f0d	164	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
11c45ebd JH	165	asm("sync;msync");
	166	*sdram_addr = 0xff;
	167	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	168	*sdram_addr2 = 0xff;
5f4c6f0d PG	169	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	170	udelay(100);
	171	}
	172
	173	/*
	174	* Issue 8 MODE-set command.
	175	*/
5f4c6f0d	176	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
11c45ebd JH	177	asm("sync;msync");
	178	*sdram_addr = 0xff;
	179	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	180	*sdram_addr2 = 0xff;
5f4c6f0d PG	181	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	182	udelay(100);
	183
	184	/*
5f4c6f0d	185	* Issue RFEN command.
11c45ebd	186	*/
5f4c6f0d	187	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
11c45ebd JH	188	asm("sync;msync");
	189	*sdram_addr = 0xff;
	190	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	191	*sdram_addr2 = 0xff;
5f4c6f0d PG	192	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	193	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	194
	195	#endif /* enable SDRAM init */
	196	}
	197
6d0f6bcf	198	#if defined(CONFIG_SYS_DRAM_TEST)
11c45ebd JH	199	int
	200	testdram(void)
	201	{
6d0f6bcf JCPV	202	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	203	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
11c45ebd JH	204	uint *p;
	205
	206	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	207	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	208	CONFIG_SYS_MEMTEST_END);
11c45ebd JH	209
	210	printf("DRAM test phase 1:\n");
	211	for (p = pstart; p < pend; p++)
	212	*p = 0xaaaaaaaa;
	213
	214	for (p = pstart; p < pend; p++) {
	215	if (*p != 0xaaaaaaaa) {
	216	printf ("DRAM test fails at: %08x\n", (uint) p);
	217	return 1;
	218	}
	219	}
	220
	221	printf("DRAM test phase 2:\n");
	222	for (p = pstart; p < pend; p++)
	223	*p = 0x55555555;
	224
	225	for (p = pstart; p < pend; p++) {
	226	if (*p != 0x55555555) {
	227	printf ("DRAM test fails at: %08x\n", (uint) p);
	228	return 1;
	229	}
	230	}
	231
	232	printf("DRAM test passed.\n");
	233	return 0;
	234	}
	235	#endif
	236
7b1f1399 PG	237	#ifdef CONFIG_PCI1
	238	static struct pci_controller pci1_hose;
	239	#endif /* CONFIG_PCI1 */
11c45ebd	240
fdc7eb90	241	#ifdef CONFIG_PCI
11c45ebd JH	242	void
	243	pci_init_board(void)
	244	{
6d0f6bcf	245	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
fdc7eb90	246	int first_free_busno = 0;
fdc7eb90 PG	247
fdc7eb90 PG	248	#ifdef CONFIG_PCI1
2d0a054d KG	249	struct fsl_pci_info pci_info;
	250	u32 devdisr = in_be32(&gur->devdisr);
	251	u32 pordevsr = in_be32(&gur->pordevsr);
	252	u32 porpllsr = in_be32(&gur->porpllsr);
	253
fdc7eb90 PG	254	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	255	uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
	256	uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	257	uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	258	uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
11c45ebd	259
8ca78f2c	260	printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
11c45ebd	261	(pci_32) ? 32 : 64,
2c40acd3 PG	262	(pci_speed == 33000000) ? "33" :
2c40acd3 PG	263	(pci_speed == 66000000) ? "66" : "unknown",
11c45ebd	264	pci_clk_sel ? "sync" : "async",
fdc7eb90 PG	265	pci_arb ? "arbiter" : "external-arbiter");
fdc7eb90 PG	266
2d0a054d KG	267	SET_STD_PCI_INFO(pci_info, 1);
	268	set_next_law(pci_info.mem_phys,
	269	law_size_bits(pci_info.mem_size), pci_info.law);
	270	set_next_law(pci_info.io_phys,
	271	law_size_bits(pci_info.io_size), pci_info.law);
	272
	273	first_free_busno = fsl_pci_init_port(&pci_info,
01471d53	274	&pci1_hose, first_free_busno);
11c45ebd	275	} else {
8ca78f2c	276	printf("PCI: disabled\n");
11c45ebd	277	}
fdc7eb90 PG	278
fdc7eb90 PG	279	puts("\n");
11c45ebd	280	#else
fdc7eb90	281	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
11c45ebd JH	282	#endif
11c45ebd JH	283
fdc7eb90	284	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
11c45ebd	285
2d0a054d	286	fsl_pcie_init_board(first_free_busno);
11c45ebd	287	}
fdc7eb90	288	#endif
11c45ebd	289
94ca0914 PG	290	int board_eth_init(bd_t *bis)
	291	{
	292	tsec_standard_init(bis);
	293	pci_eth_init(bis);
	294	return 0; /* otherwise cpu_eth_init gets run */
	295	}
	296
11c45ebd JH	297	int last_stage_init(void)
	298	{
	299	return 0;
	300	}
	301
	302	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	303	int ft_board_setup(void blob, bd_t bd)
2dba0dea KG	304	{
2dba0dea KG	305	ft_cpu_setup(blob, bd);
6525d51f KG	306
	307	#ifdef CONFIG_FSL_PCI_INIT
	308	FT_FSL_PCI_SETUP;
11c45ebd	309	#endif
e895a4b0 SG	310
e895a4b0 SG	311	return 0;
11c45ebd JH	312	}
11c45ebd JH	313	#endif