[thirdparty/u-boot.git] / board / siemens / pxm2 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Board functions for TI AM335X based pxm2 board
 * (C) Copyright 2013 Siemens Schweiz AG
 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * Based on:
 * u-boot:/board/ti/am335x/board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 */

#include <common.h>
#include <env.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include "../../../drivers/video/da8xx-fb.h"
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
#include "pmic.h"
#include <nand.h>
#include <bmp_layout.h>

#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs pxm2_ddr3_emif_reg_data = {
	.sdram_config = 0x41805332,
	.sdram_tim1 = 0x666b3c9,
	.sdram_tim2 = 0x243631ca,
	.sdram_tim3 = 0x33f,
	.emif_ddr_phy_ctlr_1 = 0x100005,
	.zq_config = 0,
	.ref_ctrl = 0x81a,
};

struct ddr_data pxm2_ddr3_data = {
	.datardsratio0 = 0x81204812,
	.datawdsratio0 = 0,
	.datafwsratio0 = 0x8020080,
	.datawrsratio0 = 0x4010040,
};

struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
	.cmd0csratio = 0x80,
	.cmd0iclkout = 0,
	.cmd1csratio = 0x80,
	.cmd1iclkout = 0,
	.cmd2csratio = 0x80,
	.cmd2iclkout = 0,
};

const struct ctrl_ioregs ioregs = {
	.cm0ioctl		= DDR_IOCTRL_VAL,
	.cm1ioctl		= DDR_IOCTRL_VAL,
	.cm2ioctl		= DDR_IOCTRL_VAL,
	.dt0ioctl		= DDR_IOCTRL_VAL,
	.dt1ioctl		= DDR_IOCTRL_VAL,
};

	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
}

/*
 * voltage switching for MPU frequency switching.
 * @module = mpu - 0, core - 1
 * @vddx_op_vol_sel = vdd voltage to set
 */

#define MPU	0
#define CORE	1

int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
{
	uchar buf[4];
	unsigned int reg_offset;

	if (module == MPU)
		reg_offset = PMIC_VDD1_OP_REG;
	else
		reg_offset = PMIC_VDD2_OP_REG;

	/* Select VDDx OP   */
	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
		return 1;

	buf[0] &= ~PMIC_OP_REG_CMD_MASK;

	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
		return 1;

	/* Configure VDDx OP  Voltage */
	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
		return 1;

	buf[0] &= ~PMIC_OP_REG_SEL_MASK;
	buf[0] |= vddx_op_vol_sel;

	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
		return 1;

	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
		return 1;

	if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
		return 1;

	return 0;
}

#define OSC     (V_OSCK/1000000)

const struct dpll_params dpll_mpu_pxm2 = {
		720, OSC-1, 1, -1, -1, -1, -1};

void spl_siemens_board_init(void)
{
	uchar buf[4];
	/*
	 * pxm2 PMIC code.  All boards currently want an MPU voltage
	 * of 1.2625V and CORE voltage of 1.1375V to operate at
	 * 720MHz.
	 */
	if (i2c_probe(PMIC_CTRL_I2C_ADDR))
		return;

	/* VDD1/2 voltage selection register access by control i/f */
	if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
		return;

	buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;

	if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
		return;

	/* Frequency switching for OPP 120 */
	if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
	    voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
		printf("voltage update failed\n");
	}
}
#endif /* if def CONFIG_SPL_BUILD */

int read_eeprom(void)
{
	/* nothing ToDo here for this board */

	return 0;
}

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_RMII,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 1,
		.phy_if		= PHY_INTERFACE_MODE_RMII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 4,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int n = 0;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_FACTORYSET
	int rv;
	if (!is_valid_ethaddr(factory_dat.mac))
		printf("Error: no valid mac address\n");
	else
		eth_env_set_enetaddr("ethaddr", factory_dat.mac);
#endif /* #ifdef CONFIG_FACTORYSET */

	/* Set rgmii mode and enable rmii clock to be sourced from chip */
	writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */

#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
	/* AUO G156XW01 V1 */
	[0] = {
		.name = "AUO_G156XW01_V1",
		.width = 1376,
		.height = 768,
		.hfp = 14,
		.hbp = 64,
		.hsw = 56,
		.vfp = 1,
		.vbp = 28,
		.vsw = 3,
		.pxl_clk = 60000000,
		.invert_pxl_clk = 0,
	},
	/* AUO B101EVN06 V0 */
	[1] = {
		.name = "AUO_B101EVN06_V0",
		.width = 1280,
		.height = 800,
		.hfp = 52,
		.hbp = 84,
		.hsw = 36,
		.vfp = 3,
		.vbp = 14,
		.vsw = 6,
		.pxl_clk = 60000000,
		.invert_pxl_clk = 0,
	},
	/*
	 * Settings from factoryset
	 * stored in EEPROM
	 */
	[2] = {
		.name = "factoryset",
		.width = 0,
		.height = 0,
		.hfp = 0,
		.hbp = 0,
		.hsw = 0,
		.vfp = 0,
		.vbp = 0,
		.vsw = 0,
		.pxl_clk = 60000000,
		.invert_pxl_clk = 0,
	},
};

static const struct display_panel disp_panel = {
	WVGA,
	32,
	16,
	COLOR_ACTIVE,
};

static const struct lcd_ctrl_config lcd_cfg = {
	&disp_panel,
	.ac_bias		= 255,
	.ac_bias_intrpt		= 0,
	.dma_burst_sz		= 16,
	.bpp			= 32,
	.fdd			= 0x80,
	.tft_alt_mode		= 0,
	.stn_565_mode		= 0,
	.mono_8bit_mode		= 0,
	.invert_line_clock	= 1,
	.invert_frm_clock	= 1,
	.sync_edge		= 0,
	.sync_ctrl		= 1,
	.raster_order		= 0,
};

static int set_gpio(int gpio, int state)
{
	gpio_request(gpio, "temp");
	gpio_direction_output(gpio, state);
	gpio_set_value(gpio, state);
	gpio_free(gpio);
	return 0;
}

static int enable_backlight(void)
{
	set_gpio(BOARD_LCD_POWER, 1);
	set_gpio(BOARD_BACK_LIGHT, 1);
	set_gpio(BOARD_TOUCH_POWER, 1);
	return 0;
}

static int enable_pwm(void)
{
	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
	struct pwmss_ecap_regs *ecap;
	int ticks = PWM_TICKS;
	int duty = PWM_DUTY;

	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
	/* enable clock */
	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
	/* TimeStam Counter register */
	writel(0xdb9, &ecap->tsctr);
	/* config period */
	writel(ticks - 1, &ecap->cap3);
	writel(ticks - 1, &ecap->cap1);
	setbits_le16(&ecap->ecctl2,
		     (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
	/* config duty */
	writel(duty, &ecap->cap2);
	writel(duty, &ecap->cap4);
	/* start */
	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
	return 0;
}

static struct dpll_regs dpll_lcd_regs = {
	.cm_clkmode_dpll = CM_WKUP + 0x98,
	.cm_idlest_dpll = CM_WKUP + 0x48,
	.cm_clksel_dpll = CM_WKUP + 0x54,
};

/* no console on this board */
int board_cfb_skip(void)
{
	return 1;
}

#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
#define PLL_GET_N(v) (v & 0x7f)

static int get_clk(struct dpll_regs *dpll_regs)
{
	unsigned int val;
	unsigned int m, n;
	int f = 0;

	val = readl(dpll_regs->cm_clksel_dpll);
	m = PLL_GET_M(val);
	n = PLL_GET_N(val);
	f = (m * V_OSCK) / n;

	return f;
};

int clk_get(int clk)
{
	return get_clk(&dpll_lcd_regs);
};

static int conf_disp_pll(int m, int n)
{
	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};

	u32 *const clk_domains[] = {
		&cmper->lcdclkctrl,
		0
	};
	u32 *const clk_modules_explicit_en[] = {
		&cmper->lcdclkctrl,
		&cmper->lcdcclkstctrl,
		&cmper->epwmss0clkctrl,
		0
	};
	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
	writel(0x0, &cmdpll->clklcdcpixelclk);

	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);

	return 0;
}

static int board_video_init(void)
{
	conf_disp_pll(24, 1);
	if (factory_dat.pxm50)
		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
	else
		da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);

	enable_pwm();
	enable_backlight();

	return 0;
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
	int ret;

	omap_nand_switch_ecc(1, 8);

#ifdef CONFIG_FACTORYSET
	if (factory_dat.asn[0] != 0) {
		char tmp[2 * MAX_STRING_LENGTH + 2];

		if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
			factory_dat.pxm50 = 1;
		else
			factory_dat.pxm50 = 0;
		sprintf(tmp, "%s_%s", factory_dat.asn,
			factory_dat.comp_version);
		ret = env_set("boardid", tmp);
		if (ret)
			printf("error setting board id\n");
	} else {
		factory_dat.pxm50 = 1;
		ret = env_set("boardid", "PXM50_1.0");
		if (ret)
			printf("error setting board id\n");
	}
	debug("PXM50: %d\n", factory_dat.pxm50);
#endif

	return 0;
}
#endif

#include "../common/board.c"
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c0dcece7 HS	2	/*
	3	* Board functions for TI AM335X based pxm2 board
	4	* (C) Copyright 2013 Siemens Schweiz AG
	5	* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
	7	* Based on:
	8	* u-boot:/board/ti/am335x/board.c
	9	*
	10	* Board functions for TI AM335X based boards
	11	*
	12	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
c0dcece7 HS	13	*/
	14
	15	#include <common.h>
9fb625ce	16	#include <env.h>
c0dcece7 HS	17	#include <errno.h>
	18	#include <spl.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/arch/hardware.h>
	21	#include <asm/arch/omap.h>
	22	#include <asm/arch/ddr_defs.h>
	23	#include <asm/arch/clock.h>
	24	#include <asm/arch/gpio.h>
	25	#include <asm/arch/mmc_host_def.h>
	26	#include <asm/arch/sys_proto.h>
	27	#include "../../../drivers/video/da8xx-fb.h"
	28	#include <asm/io.h>
	29	#include <asm/emif.h>
	30	#include <asm/gpio.h>
	31	#include <i2c.h>
	32	#include <miiphy.h>
	33	#include <cpsw.h>
	34	#include <watchdog.h>
	35	#include "board.h"
	36	#include "../common/factoryset.h"
	37	#include "pmic.h"
	38	#include <nand.h>
	39	#include <bmp_layout.h>
	40
c0dcece7 HS	41	#ifdef CONFIG_SPL_BUILD
	42	static void board_init_ddr(void)
	43	{
	44	struct emif_regs pxm2_ddr3_emif_reg_data = {
	45	.sdram_config = 0x41805332,
	46	.sdram_tim1 = 0x666b3c9,
	47	.sdram_tim2 = 0x243631ca,
	48	.sdram_tim3 = 0x33f,
	49	.emif_ddr_phy_ctlr_1 = 0x100005,
	50	.zq_config = 0,
	51	.ref_ctrl = 0x81a,
	52	};
	53
	54	struct ddr_data pxm2_ddr3_data = {
	55	.datardsratio0 = 0x81204812,
	56	.datawdsratio0 = 0,
	57	.datafwsratio0 = 0x8020080,
	58	.datawrsratio0 = 0x4010040,
c0dcece7 HS	59	};
	60
	61	struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
	62	.cmd0csratio = 0x80,
c0dcece7 HS	63	.cmd0iclkout = 0,
c0dcece7 HS	64	.cmd1csratio = 0x80,
c0dcece7 HS	65	.cmd1iclkout = 0,
c0dcece7 HS	66	.cmd2csratio = 0x80,
c0dcece7 HS	67	.cmd2iclkout = 0,
	68	};
	69
965de8b9	70	const struct ctrl_ioregs ioregs = {
9fc2ed40 ES	71	.cm0ioctl = DDR_IOCTRL_VAL,
	72	.cm1ioctl = DDR_IOCTRL_VAL,
	73	.cm2ioctl = DDR_IOCTRL_VAL,
	74	.dt0ioctl = DDR_IOCTRL_VAL,
	75	.dt1ioctl = DDR_IOCTRL_VAL,
965de8b9 LV	76	};
	77
	78	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
c0dcece7 HS	79	&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
	80	}
	81
	82	/*
	83	* voltage switching for MPU frequency switching.
	84	* @module = mpu - 0, core - 1
	85	* @vddx_op_vol_sel = vdd voltage to set
	86	*/
	87
	88	#define MPU 0
	89	#define CORE 1
	90
	91	int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
	92	{
	93	uchar buf[4];
	94	unsigned int reg_offset;
	95
	96	if (module == MPU)
	97	reg_offset = PMIC_VDD1_OP_REG;
	98	else
	99	reg_offset = PMIC_VDD2_OP_REG;
	100
	101	/* Select VDDx OP */
	102	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
	103	return 1;
	104
	105	buf[0] &= ~PMIC_OP_REG_CMD_MASK;
	106
	107	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
	108	return 1;
	109
	110	/* Configure VDDx OP Voltage */
	111	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
	112	return 1;
	113
	114	buf[0] &= ~PMIC_OP_REG_SEL_MASK;
	115	buf[0] \|= vddx_op_vol_sel;
	116
	117	if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
	118	return 1;
	119
	120	if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
	121	return 1;
	122
	123	if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
	124	return 1;
	125
	126	return 0;
	127	}
	128
	129	#define OSC (V_OSCK/1000000)
	130
	131	const struct dpll_params dpll_mpu_pxm2 = {
	132	720, OSC-1, 1, -1, -1, -1, -1};
	133
	134	void spl_siemens_board_init(void)
	135	{
	136	uchar buf[4];
	137	/*
	138	* pxm2 PMIC code. All boards currently want an MPU voltage
	139	* of 1.2625V and CORE voltage of 1.1375V to operate at
	140	* 720MHz.
	141	*/
	142	if (i2c_probe(PMIC_CTRL_I2C_ADDR))
143	return;
144
145	/* VDD1/2 voltage selection register access by control i/f */
146	if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
147	return;
148
149	buf[0] \|= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
150
151	if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
152	return;
153
154	/* Frequency switching for OPP 120 */
155	if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) \|\|
156	voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
157	printf("voltage update failed\n");
158	}
159	}
160	#endif /* if def CONFIG_SPL_BUILD */
161
162	int read_eeprom(void)
163	{
164	/* nothing ToDo here for this board */
165
166	return 0;
167	}
168
169	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
170	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
171	static void cpsw_control(int enabled)
172	{
173	/* VTP can be added here */
174
175	return;
176	}
177
178	static struct cpsw_slave_data cpsw_slaves[] = {
179	{
180	.slave_reg_ofs = 0x208,
181	.sliver_reg_ofs = 0xd80,
9c653aad	182	.phy_addr = 0,
c0dcece7 HS	183	.phy_if = PHY_INTERFACE_MODE_RMII,
	184	},
	185	{
	186	.slave_reg_ofs = 0x308,
	187	.sliver_reg_ofs = 0xdc0,
9c653aad	188	.phy_addr = 1,
c0dcece7 HS	189	.phy_if = PHY_INTERFACE_MODE_RMII,
	190	},
	191	};
	192
	193	static struct cpsw_platform_data cpsw_data = {
	194	.mdio_base = CPSW_MDIO_BASE,
	195	.cpsw_base = CPSW_BASE,
	196	.mdio_div = 0xff,
	197	.channels = 4,
	198	.cpdma_reg_ofs = 0x800,
	199	.slaves = 1,
	200	.slave_data = cpsw_slaves,
	201	.ale_reg_ofs = 0xd00,
	202	.ale_entries = 1024,
	203	.host_port_reg_ofs = 0x108,
	204	.hw_stats_reg_ofs = 0x900,
	205	.bd_ram_ofs = 0x2000,
	206	.mac_control = (1 << 5),
	207	.control = cpsw_control,
	208	.host_port_num = 0,
	209	.version = CPSW_CTRL_VERSION_2,
	210	};
	211	#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
	212
	213	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
95de1e2f	214	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
c0dcece7 HS	215	int board_eth_init(bd_t *bis)
	216	{
	217	int n = 0;
	218	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	219	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	220	struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	221	#ifdef CONFIG_FACTORYSET
	222	int rv;
0adb5b76	223	if (!is_valid_ethaddr(factory_dat.mac))
c0dcece7 HS	224	printf("Error: no valid mac address\n");
c0dcece7 HS	225	else
fd1e959e	226	eth_env_set_enetaddr("ethaddr", factory_dat.mac);
c0dcece7 HS	227	#endif /* #ifdef CONFIG_FACTORYSET */
	228
	229	/* Set rgmii mode and enable rmii clock to be sourced from chip */
60ca5ad4	230	writel(RGMII_MODE_ENABLE \| RGMII_INT_DELAY, &cdev->miisel);
c0dcece7 HS	231
	232	rv = cpsw_register(&cpsw_data);
	233	if (rv < 0)
	234	printf("Error %d registering CPSW switch\n", rv);
	235	else
	236	n += rv;
	237	#endif
	238	return n;
	239	}
	240	#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
	241
	242	#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
	243	static struct da8xx_panel lcd_panels[] = {
	244	/* AUO G156XW01 V1 */
	245	[0] = {
	246	.name = "AUO_G156XW01_V1",
	247	.width = 1376,
	248	.height = 768,
	249	.hfp = 14,
	250	.hbp = 64,
	251	.hsw = 56,
	252	.vfp = 1,
	253	.vbp = 28,
	254	.vsw = 3,
	255	.pxl_clk = 60000000,
	256	.invert_pxl_clk = 0,
	257	},
	258	/* AUO B101EVN06 V0 */
	259	[1] = {
	260	.name = "AUO_B101EVN06_V0",
	261	.width = 1280,
	262	.height = 800,
	263	.hfp = 52,
	264	.hbp = 84,
	265	.hsw = 36,
	266	.vfp = 3,
	267	.vbp = 14,
	268	.vsw = 6,
	269	.pxl_clk = 60000000,
	270	.invert_pxl_clk = 0,
	271	},
	272	/*
	273	* Settings from factoryset
	274	* stored in EEPROM
	275	*/
	276	[2] = {
	277	.name = "factoryset",
	278	.width = 0,
	279	.height = 0,
	280	.hfp = 0,
	281	.hbp = 0,
	282	.hsw = 0,
	283	.vfp = 0,
	284	.vbp = 0,
	285	.vsw = 0,
	286	.pxl_clk = 60000000,
	287	.invert_pxl_clk = 0,
	288	},
	289	};
	290
	291	static const struct display_panel disp_panel = {
	292	WVGA,
	293	32,
	294	16,
295	COLOR_ACTIVE,
296	};
297
298	static const struct lcd_ctrl_config lcd_cfg = {
299	&disp_panel,
300	.ac_bias = 255,
301	.ac_bias_intrpt = 0,
302	.dma_burst_sz = 16,
303	.bpp = 32,
304	.fdd = 0x80,
305	.tft_alt_mode = 0,
306	.stn_565_mode = 0,
307	.mono_8bit_mode = 0,
308	.invert_line_clock = 1,
309	.invert_frm_clock = 1,
310	.sync_edge = 0,
311	.sync_ctrl = 1,
312	.raster_order = 0,
313	};
314
315	static int set_gpio(int gpio, int state)
316	{
317	gpio_request(gpio, "temp");
318	gpio_direction_output(gpio, state);
319	gpio_set_value(gpio, state);
320	gpio_free(gpio);
321	return 0;
322	}
323
324	static int enable_backlight(void)
325	{
326	set_gpio(BOARD_LCD_POWER, 1);
327	set_gpio(BOARD_BACK_LIGHT, 1);
328	set_gpio(BOARD_TOUCH_POWER, 1);
329	return 0;
330	}
331
332	static int enable_pwm(void)
333	{
334	struct pwmss_regs pwmss = (struct pwmss_regs )PWMSS0_BASE;
335	struct pwmss_ecap_regs *ecap;
336	int ticks = PWM_TICKS;
337	int duty = PWM_DUTY;
338
339	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
340	/* enable clock */
341	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
342	/* TimeStam Counter register */
343	writel(0xdb9, &ecap->tsctr);
344	/* config period */
345	writel(ticks - 1, &ecap->cap3);
346	writel(ticks - 1, &ecap->cap1);
347	setbits_le16(&ecap->ecctl2,
348	(ECTRL2_MDSL_ECAP \| ECTRL2_SYNCOSEL_MASK \| 0xd0));
349	/* config duty */
350	writel(duty, &ecap->cap2);
351	writel(duty, &ecap->cap4);
352	/* start */
353	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
354	return 0;
355	}
356
357	static struct dpll_regs dpll_lcd_regs = {
358	.cm_clkmode_dpll = CM_WKUP + 0x98,
359	.cm_idlest_dpll = CM_WKUP + 0x48,
360	.cm_clksel_dpll = CM_WKUP + 0x54,
361	};
362
363	/* no console on this board */
364	int board_cfb_skip(void)
365	{
366	return 1;
367	}
368
369	#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
370	#define PLL_GET_N(v) (v & 0x7f)
371
372	static int get_clk(struct dpll_regs *dpll_regs)
373	{
374	unsigned int val;
375	unsigned int m, n;
376	int f = 0;
377
378	val = readl(dpll_regs->cm_clksel_dpll);
379	m = PLL_GET_M(val);
380	n = PLL_GET_N(val);
381	f = (m * V_OSCK) / n;
382
383	return f;
384	};
385
386	int clk_get(int clk)
387	{
388	return get_clk(&dpll_lcd_regs);
389	};
390
391	static int conf_disp_pll(int m, int n)
392	{
393	struct cm_perpll cmper = (struct cm_perpll )CM_PER;
394	struct cm_dpll cmdpll = (struct cm_dpll )CM_DPLL;
395	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
396
397	u32 *const clk_domains[] = {
398	&cmper->lcdclkctrl,
399	0
400	};
401	u32 *const clk_modules_explicit_en[] = {
402	&cmper->lcdclkctrl,
403	&cmper->lcdcclkstctrl,
404	&cmper->epwmss0clkctrl,
405	0
406	};
407	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
408	writel(0x0, &cmdpll->clklcdcpixelclk);
409
410	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
411
412	return 0;
413	}
414
415	static int board_video_init(void)
416	{
56eb3da4	417	conf_disp_pll(24, 1);
c0dcece7 HS	418	if (factory_dat.pxm50)
	419	da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
	420	else
	421	da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
	422
	423	enable_pwm();
	424	enable_backlight();
	425
	426	return 0;
	427	}
	428	#endif
0c331ebc HS	429
	430	#ifdef CONFIG_BOARD_LATE_INIT
	431	int board_late_init(void)
	432	{
	433	int ret;
	434
	435	omap_nand_switch_ecc(1, 8);
	436
	437	#ifdef CONFIG_FACTORYSET
	438	if (factory_dat.asn[0] != 0) {
	439	char tmp[2 * MAX_STRING_LENGTH + 2];
	440
	441	if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
	442	factory_dat.pxm50 = 1;
	443	else
	444	factory_dat.pxm50 = 0;
	445	sprintf(tmp, "%s_%s", factory_dat.asn,
	446	factory_dat.comp_version);
382bee57	447	ret = env_set("boardid", tmp);
0c331ebc HS	448	if (ret)
	449	printf("error setting board id\n");
	450	} else {
	451	factory_dat.pxm50 = 1;
382bee57	452	ret = env_set("boardid", "PXM50_1.0");
0c331ebc HS	453	if (ret)
	454	printf("error setting board id\n");
	455	}
	456	debug("PXM50: %d\n", factory_dat.pxm50);
	457	#endif
	458
	459	return 0;
	460	}
	461	#endif
	462
c0dcece7	463	#include "../common/board.c"