[thirdparty/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() == 3) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	/* Program freq register in System counter and enable system counter */
	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	       &iou_scntr->counter_control_register);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

void reset_cpu(ulong addr)
{
}

#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
	scsi_scan(1);
}
#endif

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;

	reg = readl(&crlapb_base->boot_mode);
	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		setenv("modeboot", "jtagboot");
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		setenv("modeboot", "qspiboot");
		puts("QSPI_MODE\n");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		setenv("modeboot", "sdboot");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		setenv("modeboot", "sdboot");
		break;
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		setenv("sdbootdev", "1");
#endif
		setenv("modeboot", "sdboot");
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		setenv("modeboot", "nandboot");
		break;
	default:
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

int usb_gadget_handle_interrupts(void)
{
	dwc3_uboot_handle_interrupt(0);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	return dwc3_uboot_init(&dwc3_device_data);
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <netdev.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
0785dfd8	12	#include <asm/arch/clk.h>
84c7204b MS	13	#include <asm/arch/hardware.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/io.h>
16fa00a7 SDPP	16	#include <usb.h>
16fa00a7 SDPP	17	#include <dwc3-uboot.h>
84c7204b MS	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	int board_init(void)
	22	{
a0736efb MS	23	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	24
84c7204b MS	25	return 0;
	26	}
	27
	28	int board_early_init_r(void)
	29	{
	30	u32 val;
	31
0785dfd8 MS	32	if (current_el() == 3) {
	33	val = readl(&crlapb_base->timestamp_ref_ctrl);
	34	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	35	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	36
0785dfd8 MS	37	/* Program freq register in System counter */
	38	writel(zynqmp_get_system_timer_freq(),
	39	&iou_scntr_secure->base_frequency_id_register);
	40	/* And enable system counter */
	41	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	42	&iou_scntr_secure->counter_control_register);
	43	}
84c7204b MS	44	/* Program freq register in System counter and enable system counter */
	45	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	46	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG \|
	47	ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	48	&iou_scntr->counter_control_register);
	49
	50	return 0;
	51	}
	52
	53	int dram_init(void)
	54	{
	55	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	56
	57	return 0;
	58	}
	59
84c7204b MS	60	void reset_cpu(ulong addr)
	61	{
	62	}
	63
6fe6f135 MS	64	#ifdef CONFIG_SCSI_AHCI_PLAT
	65	void scsi_init(void)
	66	{
	67	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
	68	scsi_scan(1);
	69	}
	70	#endif
	71
84c7204b MS	72	int board_late_init(void)
	73	{
	74	u32 reg = 0;
	75	u8 bootmode;
	76
	77	reg = readl(&crlapb_base->boot_mode);
	78	bootmode = reg & BOOT_MODES_MASK;
	79
fb90917c	80	puts("Bootmode: ");
84c7204b	81	switch (bootmode) {
0a5bcc8c	82	case JTAG_MODE:
fb90917c MS	83	puts("JTAG_MODE\n");
fb90917c MS	84	setenv("modeboot", "jtagboot");
0a5bcc8c SDPP	85	break;
	86	case QSPI_MODE_24BIT:
	87	case QSPI_MODE_32BIT:
	88	setenv("modeboot", "qspiboot");
fb90917c	89	puts("QSPI_MODE\n");
0a5bcc8c	90	break;
39c56f55	91	case EMMC_MODE:
78678fee MS	92	puts("EMMC_MODE\n");
	93	setenv("modeboot", "sdboot");
	94	break;
	95	case SD_MODE:
fb90917c	96	puts("SD_MODE\n");
84c7204b MS	97	setenv("modeboot", "sdboot");
84c7204b MS	98	break;
af813acd	99	case SD_MODE1:
fb90917c	100	puts("SD_MODE1\n");
2d9925bc MS	101	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
	102	setenv("sdbootdev", "1");
	103	#endif
	104	setenv("modeboot", "sdboot");
af813acd MS	105	break;
af813acd MS	106	case NAND_MODE:
fb90917c	107	puts("NAND_MODE\n");
af813acd MS	108	setenv("modeboot", "nandboot");
af813acd MS	109	break;
84c7204b MS	110	default:
	111	printf("Invalid Boot Mode:0x%x\n", bootmode);
	112	break;
	113	}
	114
	115	return 0;
	116	}
84696ff5 SDPP	117
	118	int checkboard(void)
	119	{
5af08556	120	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	121	return 0;
84696ff5 SDPP	122	}
16fa00a7 SDPP	123
	124	#ifdef CONFIG_USB_DWC3
	125	static struct dwc3_device dwc3_device_data = {
	126	.maximum_speed = USB_SPEED_HIGH,
	127	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	128	.dr_mode = USB_DR_MODE_PERIPHERAL,
	129	.index = 0,
	130	};
	131
	132	int usb_gadget_handle_interrupts(void)
	133	{
	134	dwc3_uboot_handle_interrupt(0);
	135	return 0;
	136	}
	137
	138	int board_usb_init(int index, enum usb_init_type init)
	139	{
	140	return dwc3_uboot_init(&dwc3_device_data);
	141	}
	142
	143	int board_usb_cleanup(int index, enum usb_init_type init)
	144	{
	145	dwc3_uboot_exit(index);
	146	return 0;
	147	}
	148	#endif