[thirdparty/u-boot.git] / cmd / mii.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
 */

/*
 * MII Utilities
 */

#include <common.h>
#include <command.h>
#include <dm.h>
#include <miiphy.h>

typedef struct _MII_field_desc_t {
	ushort hi;
	ushort lo;
	ushort mask;
	const char *name;
} MII_field_desc_t;

static const MII_field_desc_t reg_0_desc_tbl[] = {
	{ 15, 15, 0x01, "reset"                        },
	{ 14, 14, 0x01, "loopback"                     },
	{ 13,  6, 0x81, "speed selection"              }, /* special */
	{ 12, 12, 0x01, "A/N enable"                   },
	{ 11, 11, 0x01, "power-down"                   },
	{ 10, 10, 0x01, "isolate"                      },
	{  9,  9, 0x01, "restart A/N"                  },
	{  8,  8, 0x01, "duplex"                       }, /* special */
	{  7,  7, 0x01, "collision test enable"        },
	{  5,  0, 0x3f, "(reserved)"                   }
};

static const MII_field_desc_t reg_1_desc_tbl[] = {
	{ 15, 15, 0x01, "100BASE-T4 able"              },
	{ 14, 14, 0x01, "100BASE-X  full duplex able"  },
	{ 13, 13, 0x01, "100BASE-X  half duplex able"  },
	{ 12, 12, 0x01, "10 Mbps    full duplex able"  },
	{ 11, 11, 0x01, "10 Mbps    half duplex able"  },
	{ 10, 10, 0x01, "100BASE-T2 full duplex able"  },
	{  9,  9, 0x01, "100BASE-T2 half duplex able"  },
	{  8,  8, 0x01, "extended status"              },
	{  7,  7, 0x01, "(reserved)"                   },
	{  6,  6, 0x01, "MF preamble suppression"      },
	{  5,  5, 0x01, "A/N complete"                 },
	{  4,  4, 0x01, "remote fault"                 },
	{  3,  3, 0x01, "A/N able"                     },
	{  2,  2, 0x01, "link status"                  },
	{  1,  1, 0x01, "jabber detect"                },
	{  0,  0, 0x01, "extended capabilities"        },
};

static const MII_field_desc_t reg_2_desc_tbl[] = {
	{ 15,  0, 0xffff, "OUI portion"                },
};

static const MII_field_desc_t reg_3_desc_tbl[] = {
	{ 15, 10, 0x3f, "OUI portion"                },
	{  9,  4, 0x3f, "manufacturer part number"   },
	{  3,  0, 0x0f, "manufacturer rev. number"   },
};

static const MII_field_desc_t reg_4_desc_tbl[] = {
	{ 15, 15, 0x01, "next page able"               },
	{ 14, 14, 0x01, "(reserved)"                   },
	{ 13, 13, 0x01, "remote fault"                 },
	{ 12, 12, 0x01, "(reserved)"                   },
	{ 11, 11, 0x01, "asymmetric pause"             },
	{ 10, 10, 0x01, "pause enable"                 },
	{  9,  9, 0x01, "100BASE-T4 able"              },
	{  8,  8, 0x01, "100BASE-TX full duplex able"  },
	{  7,  7, 0x01, "100BASE-TX able"              },
	{  6,  6, 0x01, "10BASE-T   full duplex able"  },
	{  5,  5, 0x01, "10BASE-T   able"              },
	{  4,  0, 0x1f, "selector"                     },
};

static const MII_field_desc_t reg_5_desc_tbl[] = {
	{ 15, 15, 0x01, "next page able"               },
	{ 14, 14, 0x01, "acknowledge"                  },
	{ 13, 13, 0x01, "remote fault"                 },
	{ 12, 12, 0x01, "(reserved)"                   },
	{ 11, 11, 0x01, "asymmetric pause able"        },
	{ 10, 10, 0x01, "pause able"                   },
	{  9,  9, 0x01, "100BASE-T4 able"              },
	{  8,  8, 0x01, "100BASE-X full duplex able"   },
	{  7,  7, 0x01, "100BASE-TX able"              },
	{  6,  6, 0x01, "10BASE-T full duplex able"    },
	{  5,  5, 0x01, "10BASE-T able"                },
	{  4,  0, 0x1f, "partner selector"             },
};

static const MII_field_desc_t reg_9_desc_tbl[] = {
	{ 15, 13, 0x07, "test mode"		       },
	{ 12, 12, 0x01, "manual master/slave enable"   },
	{ 11, 11, 0x01, "manual master/slave value"    },
	{ 10, 10, 0x01, "multi/single port"            },
	{  9,  9, 0x01, "1000BASE-T full duplex able"  },
	{  8,  8, 0x01, "1000BASE-T half duplex able"  },
	{  7,  7, 0x01, "automatic TDR on link down"   },
	{  6,  6, 0x7f, "(reserved)"                   },
};

static const MII_field_desc_t reg_10_desc_tbl[] = {
	{ 15, 15, 0x01, "master/slave config fault"    },
	{ 14, 14, 0x01, "master/slave config result"   },
	{ 13, 13, 0x01, "local receiver status OK"     },
	{ 12, 12, 0x01, "remote receiver status OK"    },
	{ 11, 11, 0x01, "1000BASE-T full duplex able"  },
	{ 10, 10, 0x01, "1000BASE-T half duplex able"  },
	{  9,  8, 0x03, "(reserved)"                   },
	{  7,  0, 0xff, "1000BASE-T idle error counter"},
};

typedef struct _MII_reg_desc_t {
	ushort regno;
	const MII_field_desc_t *pdesc;
	ushort len;
	const char *name;
} MII_reg_desc_t;

static const MII_reg_desc_t mii_reg_desc_tbl[] = {
	{ MII_BMCR,      reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
		"PHY control register" },
	{ MII_BMSR,      reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
		"PHY status register" },
	{ MII_PHYSID1,   reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
		"PHY ID 1 register" },
	{ MII_PHYSID2,   reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
		"PHY ID 2 register" },
	{ MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
		"Autonegotiation advertisement register" },
	{ MII_LPA,       reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
		"Autonegotiation partner abilities register" },
	{ MII_CTRL1000,	 reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
		"1000BASE-T control register" },
	{ MII_STAT1000,	 reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
		"1000BASE-T status register" },
};

static void dump_reg(
	ushort             regval,
	const MII_reg_desc_t *prd);

static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
			  ushort regval);

static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
{
	ulong i;

	for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
		const uchar reg = mii_reg_desc_tbl[i].regno;

		if (reg >= reglo && reg <= reghi)
			dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
	}
}

/* Print out field position, value, name */
static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
{
	if (pdesc->hi == pdesc->lo)
		printf("%2u   ", pdesc->lo);
	else
		printf("%2u-%2u", pdesc->hi, pdesc->lo);

	printf(" = %5u	  %s", (regval >> pdesc->lo) & pdesc->mask,
	       pdesc->name);
}

static void dump_reg(
	ushort             regval,
	const MII_reg_desc_t *prd)
{
	ulong i;
	ushort mask_in_place;
	const MII_field_desc_t *pdesc;

	printf("%u.     (%04hx)                 -- %s --\n",
		prd->regno, regval, prd->name);

	for (i = 0; i < prd->len; i++) {
		pdesc = &prd->pdesc[i];

		mask_in_place = pdesc->mask << pdesc->lo;

		printf("  (%04hx:%04x) %u.",
		       mask_in_place,
		       regval & mask_in_place,
		       prd->regno);

		if (!special_field(prd->regno, pdesc, regval))
			dump_field(pdesc, regval);
		printf("\n");

	}
	printf("\n");
}

/* Special fields:
** 0.6,13
** 0.8
** 2.15-0
** 3.15-0
** 4.4-0
** 5.4-0
*/

static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
			  ushort regval)
{
	const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;

	if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
		ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100);
		printf("%2u,%2u =   b%u%u    speed selection = %s Mbps",
			6, 13,
			(regval >>  6) & 1,
			(regval >> 13) & 1,
			speed_bits == BMCR_SPEED1000 ? "1000" :
			speed_bits == BMCR_SPEED100  ? "100" :
			"10");
		return 1;
	}

	else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
		dump_field(pdesc, regval);
		printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
		return 1;
	}

	else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
		dump_field(pdesc, regval);
		printf(" = %s",
		       sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
		       sel_bits == PHY_ANLPAR_PSB_802_9 ?
		       "IEEE 802.9 ISLAN-16T" : "???");
		return 1;
	}

	else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
		dump_field(pdesc, regval);
		printf(" = %s",
		       sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
		       sel_bits == PHY_ANLPAR_PSB_802_9 ?
		       "IEEE 802.9 ISLAN-16T" : "???");
		return 1;
	}

	return 0;
}

static char last_op[2];
static uint last_data;
static uint last_addr_lo;
static uint last_addr_hi;
static uint last_reg_lo;
static uint last_reg_hi;
static uint last_mask;

static void extract_range(
	char * input,
	unsigned char * plo,
	unsigned char * phi)
{
	char * end;
	*plo = hextoul(input, &end);
	if (*end == '-') {
		end++;
		*phi = hextoul(end, NULL);
	}
	else {
		*phi = *plo;
	}
}

/* ---------------------------------------------------------------- */
static int do_mii(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	char		op[2];
	unsigned char	addrlo, addrhi, reglo, reghi;
	unsigned char	addr, reg;
	unsigned short	data, mask;
	int		rcode = 0;
	const char	*devname;

	if (argc < 2)
		return CMD_RET_USAGE;

#if defined(CONFIG_MII_INIT)
	mii_init ();
#endif

	/*
	 * We use the last specified parameters, unless new ones are
	 * entered.
	 */
	op[0] = last_op[0];
	op[1] = last_op[1];
	addrlo = last_addr_lo;
	addrhi = last_addr_hi;
	reglo  = last_reg_lo;
	reghi  = last_reg_hi;
	data   = last_data;
	mask   = last_mask;

	if ((flag & CMD_FLAG_REPEAT) == 0) {
		op[0] = argv[1][0];
		if (strlen(argv[1]) > 1)
			op[1] = argv[1][1];
		else
			op[1] = '\0';

		if (argc >= 3)
			extract_range(argv[2], &addrlo, &addrhi);
		if (argc >= 4)
			extract_range(argv[3], &reglo, &reghi);
		if (argc >= 5)
			data = hextoul(argv[4], NULL);
		if (argc >= 6)
			mask = hextoul(argv[5], NULL);
	}

	if (addrhi > 31 && strncmp(op, "de", 2)) {
		printf("Incorrect PHY address. Range should be 0-31\n");
		return CMD_RET_USAGE;
	}

	/* use current device */
	devname = miiphy_get_current_dev();

	/*
	 * check info/read/write.
	 */
	if (op[0] == 'i') {
		unsigned char j, start, end;
		unsigned int oui;
		unsigned char model;
		unsigned char rev;

		/*
		 * Look for any and all PHYs.  Valid addresses are 0..31.
		 */
		if (argc >= 3) {
			start = addrlo; end = addrhi;
		} else {
			start = 0; end = 31;
		}

		for (j = start; j <= end; j++) {
			if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
				printf("PHY 0x%02X: "
					"OUI = 0x%04X, "
					"Model = 0x%02X, "
					"Rev = 0x%02X, "
					"%3dbase%s, %s\n",
					j, oui, model, rev,
					miiphy_speed (devname, j),
					miiphy_is_1000base_x (devname, j)
						? "X" : "T",
					(miiphy_duplex (devname, j) == FULL)
						? "FDX" : "HDX");
			}
		}
	} else if (op[0] == 'r') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				data = 0xffff;
				if (miiphy_read (devname, addr, reg, &data) != 0) {
					printf(
					"Error reading from the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				} else {
					if ((addrlo != addrhi) || (reglo != reghi))
						printf("addr=%02x reg=%02x data=",
							(uint)addr, (uint)reg);
					printf("%04X\n", data & 0x0000FFFF);
				}
			}
			if ((addrlo != addrhi) && (reglo != reghi))
				printf("\n");
		}
	} else if (op[0] == 'w') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				if (miiphy_write (devname, addr, reg, data) != 0) {
					printf("Error writing to the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				}
			}
		}
	} else if (op[0] == 'm') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				unsigned short val = 0;
				if (miiphy_read(devname, addr,
						reg, &val)) {
					printf("Error reading from the PHY");
					printf(" addr=%02x", addr);
					printf(" reg=%02x\n", reg);
					rcode = 1;
				} else {
					val = (val & ~mask) | (data & mask);
					if (miiphy_write(devname, addr,
							 reg, val)) {
						printf("Error writing to the PHY");
						printf(" addr=%02x", addr);
						printf(" reg=%02x\n", reg);
						rcode = 1;
					}
				}
			}
		}
	} else if (strncmp(op, "du", 2) == 0) {
		ushort regs[MII_STAT1000 + 1];  /* Last reg is 0x0a */
		int ok = 1;
		if (reglo > MII_STAT1000 || reghi > MII_STAT1000) {
			printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
			return 1;
		}
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				if (miiphy_read(devname, addr, reg,
						&regs[reg - reglo]) != 0) {
					ok = 0;
					printf(
					"Error reading from the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				}
			}
			if (ok)
				MII_dump(regs, reglo, reghi);
			printf("\n");
		}
	} else if (strncmp(op, "de", 2) == 0) {
		if (argc == 2)
			miiphy_listdev ();
		else
			miiphy_set_current_dev (argv[2]);
	} else {
		return CMD_RET_USAGE;
	}

	/*
	 * Save the parameters for repeats.
	 */
	last_op[0] = op[0];
	last_op[1] = op[1];
	last_addr_lo = addrlo;
	last_addr_hi = addrhi;
	last_reg_lo  = reglo;
	last_reg_hi  = reghi;
	last_data    = data;
	last_mask    = mask;

	return rcode;
}

/***************************************************/

U_BOOT_CMD(
	mii, 6, 1, do_mii,
	"MII utility commands",
	"device                            - list available devices\n"
	"mii device <devname>                  - set current device\n"
	"mii info   <addr>                     - display MII PHY info\n"
	"mii read   <addr> <reg>               - read  MII PHY <addr> register <reg>\n"
	"mii write  <addr> <reg> <data>        - write MII PHY <addr> register <reg>\n"
	"mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
	"                                        updating bits identified in <mask>\n"
	"mii dump   <addr> <reg>               - pretty-print <addr> <reg> (0-5 only)\n"
	"Addr and/or reg may be ranges, e.g. 2-7."
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dd7d41f0 WD	2	/*
	3	* (C) Copyright 2001
	4	* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
dd7d41f0 WD	5	*/
	6
	7	/*
	8	* MII Utilities
	9	*/
	10
	11	#include <common.h>
	12	#include <command.h>
2a64ada7	13	#include <dm.h>
e35745bb WD	14	#include <miiphy.h>
e35745bb WD	15
2471111d WD	16	typedef struct _MII_field_desc_t {
	17	ushort hi;
	18	ushort lo;
	19	ushort mask;
4ef3231b	20	const char *name;
2471111d WD	21	} MII_field_desc_t;
2471111d WD	22
3a5ee0b1	23	static const MII_field_desc_t reg_0_desc_tbl[] = {
2471111d WD	24	{ 15, 15, 0x01, "reset" },
	25	{ 14, 14, 0x01, "loopback" },
	26	{ 13, 6, 0x81, "speed selection" }, /* special */
	27	{ 12, 12, 0x01, "A/N enable" },
	28	{ 11, 11, 0x01, "power-down" },
	29	{ 10, 10, 0x01, "isolate" },
	30	{ 9, 9, 0x01, "restart A/N" },
	31	{ 8, 8, 0x01, "duplex" }, /* special */
	32	{ 7, 7, 0x01, "collision test enable" },
	33	{ 5, 0, 0x3f, "(reserved)" }
	34	};
	35
3a5ee0b1	36	static const MII_field_desc_t reg_1_desc_tbl[] = {
2471111d WD	37	{ 15, 15, 0x01, "100BASE-T4 able" },
	38	{ 14, 14, 0x01, "100BASE-X full duplex able" },
	39	{ 13, 13, 0x01, "100BASE-X half duplex able" },
	40	{ 12, 12, 0x01, "10 Mbps full duplex able" },
	41	{ 11, 11, 0x01, "10 Mbps half duplex able" },
	42	{ 10, 10, 0x01, "100BASE-T2 full duplex able" },
	43	{ 9, 9, 0x01, "100BASE-T2 half duplex able" },
	44	{ 8, 8, 0x01, "extended status" },
	45	{ 7, 7, 0x01, "(reserved)" },
	46	{ 6, 6, 0x01, "MF preamble suppression" },
	47	{ 5, 5, 0x01, "A/N complete" },
	48	{ 4, 4, 0x01, "remote fault" },
	49	{ 3, 3, 0x01, "A/N able" },
	50	{ 2, 2, 0x01, "link status" },
	51	{ 1, 1, 0x01, "jabber detect" },
	52	{ 0, 0, 0x01, "extended capabilities" },
	53	};
	54
3a5ee0b1	55	static const MII_field_desc_t reg_2_desc_tbl[] = {
2471111d WD	56	{ 15, 0, 0xffff, "OUI portion" },
	57	};
	58
3a5ee0b1	59	static const MII_field_desc_t reg_3_desc_tbl[] = {
2471111d WD	60	{ 15, 10, 0x3f, "OUI portion" },
	61	{ 9, 4, 0x3f, "manufacturer part number" },
	62	{ 3, 0, 0x0f, "manufacturer rev. number" },
	63	};
	64
3a5ee0b1	65	static const MII_field_desc_t reg_4_desc_tbl[] = {
2471111d	66	{ 15, 15, 0x01, "next page able" },
57d33d4b	67	{ 14, 14, 0x01, "(reserved)" },
2471111d	68	{ 13, 13, 0x01, "remote fault" },
57d33d4b	69	{ 12, 12, 0x01, "(reserved)" },
2471111d WD	70	{ 11, 11, 0x01, "asymmetric pause" },
	71	{ 10, 10, 0x01, "pause enable" },
	72	{ 9, 9, 0x01, "100BASE-T4 able" },
	73	{ 8, 8, 0x01, "100BASE-TX full duplex able" },
	74	{ 7, 7, 0x01, "100BASE-TX able" },
	75	{ 6, 6, 0x01, "10BASE-T full duplex able" },
	76	{ 5, 5, 0x01, "10BASE-T able" },
4ef3231b	77	{ 4, 0, 0x1f, "selector" },
2471111d WD	78	};
2471111d WD	79
3a5ee0b1	80	static const MII_field_desc_t reg_5_desc_tbl[] = {
2471111d WD	81	{ 15, 15, 0x01, "next page able" },
	82	{ 14, 14, 0x01, "acknowledge" },
	83	{ 13, 13, 0x01, "remote fault" },
	84	{ 12, 12, 0x01, "(reserved)" },
	85	{ 11, 11, 0x01, "asymmetric pause able" },
	86	{ 10, 10, 0x01, "pause able" },
	87	{ 9, 9, 0x01, "100BASE-T4 able" },
	88	{ 8, 8, 0x01, "100BASE-X full duplex able" },
	89	{ 7, 7, 0x01, "100BASE-TX able" },
	90	{ 6, 6, 0x01, "10BASE-T full duplex able" },
	91	{ 5, 5, 0x01, "10BASE-T able" },
4ef3231b	92	{ 4, 0, 0x1f, "partner selector" },
2471111d	93	};
4ef3231b	94
95637868 TP	95	static const MII_field_desc_t reg_9_desc_tbl[] = {
	96	{ 15, 13, 0x07, "test mode" },
	97	{ 12, 12, 0x01, "manual master/slave enable" },
	98	{ 11, 11, 0x01, "manual master/slave value" },
	99	{ 10, 10, 0x01, "multi/single port" },
	100	{ 9, 9, 0x01, "1000BASE-T full duplex able" },
	101	{ 8, 8, 0x01, "1000BASE-T half duplex able" },
	102	{ 7, 7, 0x01, "automatic TDR on link down" },
	103	{ 6, 6, 0x7f, "(reserved)" },
	104	};
	105
	106	static const MII_field_desc_t reg_10_desc_tbl[] = {
	107	{ 15, 15, 0x01, "master/slave config fault" },
	108	{ 14, 14, 0x01, "master/slave config result" },
	109	{ 13, 13, 0x01, "local receiver status OK" },
	110	{ 12, 12, 0x01, "remote receiver status OK" },
	111	{ 11, 11, 0x01, "1000BASE-T full duplex able" },
	112	{ 10, 10, 0x01, "1000BASE-T half duplex able" },
	113	{ 9, 8, 0x03, "(reserved)" },
	114	{ 7, 0, 0xff, "1000BASE-T idle error counter"},
	115	};
	116
4ef3231b TP	117	typedef struct _MII_reg_desc_t {
4ef3231b TP	118	ushort regno;
3a5ee0b1	119	const MII_field_desc_t *pdesc;
2471111d	120	ushort len;
4ef3231b TP	121	const char *name;
	122	} MII_reg_desc_t;
	123
	124	static const MII_reg_desc_t mii_reg_desc_tbl[] = {
	125	{ MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
	126	"PHY control register" },
	127	{ MII_BMSR, reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
	128	"PHY status register" },
	129	{ MII_PHYSID1, reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
	130	"PHY ID 1 register" },
	131	{ MII_PHYSID2, reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
	132	"PHY ID 2 register" },
	133	{ MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
	134	"Autonegotiation advertisement register" },
	135	{ MII_LPA, reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
	136	"Autonegotiation partner abilities register" },
95637868 TP	137	{ MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
	138	"1000BASE-T control register" },
	139	{ MII_STAT1000, reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
	140	"1000BASE-T status register" },
2471111d WD	141	};
	142
	143	static void dump_reg(
	144	ushort regval,
4ef3231b TP	145	const MII_reg_desc_t *prd);
	146
	147	static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
	148	ushort regval);
	149
	150	static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
2471111d WD	151	{
	152	ulong i;
	153
4ef3231b TP	154	for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
	155	const uchar reg = mii_reg_desc_tbl[i].regno;
	156
	157	if (reg >= reglo && reg <= reghi)
	158	dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
2471111d WD	159	}
	160	}
	161
4ef3231b TP	162	/* Print out field position, value, name */
	163	static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
	164	{
	165	if (pdesc->hi == pdesc->lo)
	166	printf("%2u ", pdesc->lo);
	167	else
	168	printf("%2u-%2u", pdesc->hi, pdesc->lo);
	169
	170	printf(" = %5u %s", (regval >> pdesc->lo) & pdesc->mask,
	171	pdesc->name);
	172	}
	173
2471111d WD	174	static void dump_reg(
2471111d WD	175	ushort regval,
4ef3231b	176	const MII_reg_desc_t *prd)
2471111d WD	177	{
	178	ulong i;
	179	ushort mask_in_place;
3a5ee0b1	180	const MII_field_desc_t *pdesc;
2471111d WD	181
	182	printf("%u. (%04hx) -- %s --\n",
	183	prd->regno, regval, prd->name);
	184
4ef3231b TP	185	for (i = 0; i < prd->len; i++) {
4ef3231b TP	186	pdesc = &prd->pdesc[i];
2471111d WD	187
	188	mask_in_place = pdesc->mask << pdesc->lo;
	189
c68112f3 JH	190	printf(" (%04hx:%04x) %u.",
	191	mask_in_place,
	192	regval & mask_in_place,
	193	prd->regno);
2471111d	194
4ef3231b TP	195	if (!special_field(prd->regno, pdesc, regval))
4ef3231b TP	196	dump_field(pdesc, regval);
2471111d WD	197	printf("\n");
	198
	199	}
	200	printf("\n");
	201	}
	202
	203	/* Special fields:
	204	** 0.6,13
	205	** 0.8
	206	** 2.15-0
	207	** 3.15-0
	208	** 4.4-0
	209	** 5.4-0
	210	*/
	211
4ef3231b TP	212	static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
4ef3231b TP	213	ushort regval)
2471111d	214	{
4ef3231b TP	215	const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
4ef3231b TP	216
8ef583a0 MF	217	if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
8ef583a0 MF	218	ushort speed_bits = regval & (BMCR_SPEED1000 \| BMCR_SPEED100);
2471111d WD	219	printf("%2u,%2u = b%u%u speed selection = %s Mbps",
	220	6, 13,
	221	(regval >> 6) & 1,
	222	(regval >> 13) & 1,
8ef583a0 MF	223	speed_bits == BMCR_SPEED1000 ? "1000" :
	224	speed_bits == BMCR_SPEED100 ? "100" :
	225	"10");
2471111d WD	226	return 1;
	227	}
	228
8ef583a0	229	else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
4ef3231b TP	230	dump_field(pdesc, regval);
4ef3231b TP	231	printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
2471111d WD	232	return 1;
	233	}
	234
8ef583a0	235	else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
4ef3231b TP	236	dump_field(pdesc, regval);
	237	printf(" = %s",
	238	sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
	239	sel_bits == PHY_ANLPAR_PSB_802_9 ?
	240	"IEEE 802.9 ISLAN-16T" : "???");
2471111d WD	241	return 1;
	242	}
	243
8ef583a0	244	else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
4ef3231b TP	245	dump_field(pdesc, regval);
	246	printf(" = %s",
	247	sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
	248	sel_bits == PHY_ANLPAR_PSB_802_9 ?
	249	"IEEE 802.9 ISLAN-16T" : "???");
2471111d WD	250	return 1;
	251	}
	252
	253	return 0;
	254	}
	255
3a5ee0b1 MF	256	static char last_op[2];
	257	static uint last_data;
	258	static uint last_addr_lo;
	259	static uint last_addr_hi;
	260	static uint last_reg_lo;
	261	static uint last_reg_hi;
a095f047	262	static uint last_mask;
2471111d WD	263
	264	static void extract_range(
	265	char * input,
	266	unsigned char * plo,
	267	unsigned char * phi)
	268	{
	269	char * end;
7e5f460e	270	*plo = hextoul(input, &end);
2471111d WD	271	if (*end == '-') {
2471111d WD	272	end++;
7e5f460e	273	*phi = hextoul(end, NULL);
2471111d WD	274	}
	275	else {
	276	phi = plo;
	277	}
	278	}
	279
5cf91d6b	280	/* ---------------------------------------------------------------- */
09140113	281	static int do_mii(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
2471111d	282	{
63ff004c	283	char op[2];
2471111d	284	unsigned char addrlo, addrhi, reglo, reghi;
2b792afc	285	unsigned char addr, reg;
a095f047	286	unsigned short data, mask;
2471111d	287	int rcode = 0;
5700bb63	288	const char *devname;
2471111d	289
47e26b1b	290	if (argc < 2)
4c12eeb8	291	return CMD_RET_USAGE;
b9173af7	292
0f3ba7e9	293	#if defined(CONFIG_MII_INIT)
2471111d WD	294	mii_init ();
	295	#endif
	296
	297	/*
	298	* We use the last specified parameters, unless new ones are
	299	* entered.
	300	*/
63ff004c MB	301	op[0] = last_op[0];
63ff004c MB	302	op[1] = last_op[1];
2471111d WD	303	addrlo = last_addr_lo;
	304	addrhi = last_addr_hi;
	305	reglo = last_reg_lo;
	306	reghi = last_reg_hi;
	307	data = last_data;
a095f047	308	mask = last_mask;
2471111d WD	309
2471111d WD	310	if ((flag & CMD_FLAG_REPEAT) == 0) {
63ff004c MB	311	op[0] = argv[1][0];
	312	if (strlen(argv[1]) > 1)
	313	op[1] = argv[1][1];
	314	else
	315	op[1] = '\0';
	316
2471111d WD	317	if (argc >= 3)
	318	extract_range(argv[2], &addrlo, &addrhi);
	319	if (argc >= 4)
	320	extract_range(argv[3], &reglo, &reghi);
	321	if (argc >= 5)
7e5f460e	322	data = hextoul(argv[4], NULL);
a095f047	323	if (argc >= 6)
7e5f460e	324	mask = hextoul(argv[5], NULL);
2471111d WD	325	}
2471111d WD	326
fb265a74	327	if (addrhi > 31 && strncmp(op, "de", 2)) {
bdaeb8f2 MS	328	printf("Incorrect PHY address. Range should be 0-31\n");
	329	return CMD_RET_USAGE;
	330	}
	331
63ff004c MB	332	/* use current device */
	333	devname = miiphy_get_current_dev();
	334
2471111d WD	335	/*
	336	* check info/read/write.
	337	*/
63ff004c	338	if (op[0] == 'i') {
2471111d WD	339	unsigned char j, start, end;
	340	unsigned int oui;
	341	unsigned char model;
	342	unsigned char rev;
	343
	344	/*
	345	* Look for any and all PHYs. Valid addresses are 0..31.
	346	*/
	347	if (argc >= 3) {
2b792afc	348	start = addrlo; end = addrhi;
2471111d	349	} else {
2b792afc	350	start = 0; end = 31;
2471111d WD	351	}
2471111d WD	352
2b792afc	353	for (j = start; j <= end; j++) {
63ff004c	354	if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
2471111d WD	355	printf("PHY 0x%02X: "
	356	"OUI = 0x%04X, "
	357	"Model = 0x%02X, "
	358	"Rev = 0x%02X, "
71bc6e64	359	"%3dbase%s, %s\n",
2471111d	360	j, oui, model, rev,
63ff004c	361	miiphy_speed (devname, j),
71bc6e64 LJ	362	miiphy_is_1000base_x (devname, j)
71bc6e64 LJ	363	? "X" : "T",
63ff004c MB	364	(miiphy_duplex (devname, j) == FULL)
63ff004c MB	365	? "FDX" : "HDX");
2471111d WD	366	}
2471111d WD	367	}
63ff004c	368	} else if (op[0] == 'r') {
2471111d WD	369	for (addr = addrlo; addr <= addrhi; addr++) {
	370	for (reg = reglo; reg <= reghi; reg++) {
	371	data = 0xffff;
63ff004c	372	if (miiphy_read (devname, addr, reg, &data) != 0) {
2471111d WD	373	printf(
	374	"Error reading from the PHY addr=%02x reg=%02x\n",
	375	addr, reg);
	376	rcode = 1;
2b792afc	377	} else {
2471111d WD	378	if ((addrlo != addrhi) \|\| (reglo != reghi))
	379	printf("addr=%02x reg=%02x data=",
	380	(uint)addr, (uint)reg);
	381	printf("%04X\n", data & 0x0000FFFF);
	382	}
	383	}
	384	if ((addrlo != addrhi) && (reglo != reghi))
	385	printf("\n");
	386	}
63ff004c	387	} else if (op[0] == 'w') {
2471111d WD	388	for (addr = addrlo; addr <= addrhi; addr++) {
2471111d WD	389	for (reg = reglo; reg <= reghi; reg++) {
63ff004c	390	if (miiphy_write (devname, addr, reg, data) != 0) {
2471111d WD	391	printf("Error writing to the PHY addr=%02x reg=%02x\n",
	392	addr, reg);
	393	rcode = 1;
	394	}
	395	}
	396	}
a095f047 TJ	397	} else if (op[0] == 'm') {
	398	for (addr = addrlo; addr <= addrhi; addr++) {
	399	for (reg = reglo; reg <= reghi; reg++) {
	400	unsigned short val = 0;
	401	if (miiphy_read(devname, addr,
	402	reg, &val)) {
	403	printf("Error reading from the PHY");
	404	printf(" addr=%02x", addr);
	405	printf(" reg=%02x\n", reg);
	406	rcode = 1;
	407	} else {
	408	val = (val & ~mask) \| (data & mask);
	409	if (miiphy_write(devname, addr,
	410	reg, val)) {
	411	printf("Error writing to the PHY");
	412	printf(" addr=%02x", addr);
	413	printf(" reg=%02x\n", reg);
	414	rcode = 1;
	415	}
	416	}
	417	}
	418	}
63ff004c	419	} else if (strncmp(op, "du", 2) == 0) {
95637868	420	ushort regs[MII_STAT1000 + 1]; /* Last reg is 0x0a */
2471111d	421	int ok = 1;
95637868 TP	422	if (reglo > MII_STAT1000 \|\| reghi > MII_STAT1000) {
95637868 TP	423	printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
2471111d WD	424	return 1;
	425	}
	426	for (addr = addrlo; addr <= addrhi; addr++) {
4ef3231b TP	427	for (reg = reglo; reg <= reghi; reg++) {
	428	if (miiphy_read(devname, addr, reg,
	429	&regs[reg - reglo]) != 0) {
2471111d WD	430	ok = 0;
	431	printf(
	432	"Error reading from the PHY addr=%02x reg=%02x\n",
	433	addr, reg);
	434	rcode = 1;
	435	}
	436	}
	437	if (ok)
4ef3231b	438	MII_dump(regs, reglo, reghi);
2471111d WD	439	printf("\n");
2471111d WD	440	}
63ff004c MB	441	} else if (strncmp(op, "de", 2) == 0) {
	442	if (argc == 2)
	443	miiphy_listdev ();
	444	else
	445	miiphy_set_current_dev (argv[2]);
2471111d	446	} else {
4c12eeb8	447	return CMD_RET_USAGE;
2471111d WD	448	}
	449
	450	/*
	451	* Save the parameters for repeats.
	452	*/
63ff004c MB	453	last_op[0] = op[0];
63ff004c MB	454	last_op[1] = op[1];
2471111d WD	455	last_addr_lo = addrlo;
	456	last_addr_hi = addrhi;
	457	last_reg_lo = reglo;
	458	last_reg_hi = reghi;
	459	last_data = data;
a095f047	460	last_mask = mask;
2471111d WD	461
	462	return rcode;
	463	}
	464
	465	/***************************************************/
	466
	467	U_BOOT_CMD(
a095f047	468	mii, 6, 1, do_mii,
2fb2604d	469	"MII utility commands",
a095f047 TJ	470	"device - list available devices\n"
	471	"mii device <devname> - set current device\n"
	472	"mii info <addr> - display MII PHY info\n"
	473	"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
	474	"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
	475	"mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
	476	" updating bits identified in <mask>\n"
	477	"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
a89c33db	478	"Addr and/or reg may be ranges, e.g. 2-7."
2471111d	479	);