[thirdparty/u-boot.git] / drivers / ddr / fsl / ddr3_dimm_params.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
 *	Dave Liu <daveliu@freescale.com>
 *
 * calculate the organization and timing parameter
 * from ddr3 spd, please refer to the spec
 * JEDEC standard No.21-C 4_01_02_11R18.pdf
 */

#include <common.h>
#include <fsl_ddr_sdram.h>

#include <fsl_ddr.h>

/*
 * Calculate the Density of each Physical Rank.
 * Returned size is in bytes.
 *
 * each rank size =
 * sdram capacity(bit) / 8 * primary bus width / sdram width
 *
 * where: sdram capacity  = spd byte4[3:0]
 *        primary bus width = spd byte8[2:0]
 *        sdram width = spd byte7[2:0]
 *
 * SPD byte4 - sdram density and banks
 *	bit[3:0]	size(bit)	size(byte)
 *	0000		256Mb		32MB
 *	0001		512Mb		64MB
 *	0010		1Gb		128MB
 *	0011		2Gb		256MB
 *	0100		4Gb		512MB
 *	0101		8Gb		1GB
 *	0110		16Gb		2GB
 *
 * SPD byte8 - module memory bus width
 * 	bit[2:0]	primary bus width
 *	000		8bits
 * 	001		16bits
 * 	010		32bits
 * 	011		64bits
 *
 * SPD byte7 - module organiztion
 * 	bit[2:0]	sdram device width
 * 	000		4bits
 * 	001		8bits
 * 	010		16bits
 * 	011		32bits
 *
 */
static unsigned long long
compute_ranksize(const ddr3_spd_eeprom_t *spd)
{
	unsigned long long bsize;

	int nbit_sdram_cap_bsize = 0;
	int nbit_primary_bus_width = 0;
	int nbit_sdram_width = 0;

	if ((spd->density_banks & 0xf) < 7)
		nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
	if ((spd->bus_width & 0x7) < 4)
		nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
	if ((spd->organization & 0x7) < 4)
		nbit_sdram_width = (spd->organization & 0x7) + 2;

	bsize = 1ULL << (nbit_sdram_cap_bsize - 3
		    + nbit_primary_bus_width - nbit_sdram_width);

	debug("DDR: DDR III rank density = 0x%16llx\n", bsize);

	return bsize;
}

/*
 * ddr_compute_dimm_parameters for DDR3 SPD
 *
 * Compute DIMM parameters based upon the SPD information in spd.
 * Writes the results to the dimm_params_t structure pointed by pdimm.
 *
 */
unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
					 const ddr3_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number)
{
	unsigned int retval;
	unsigned int mtb_ps;
	int ftb_10th_ps;
	int i;

	if (spd->mem_type) {
		if (spd->mem_type != SPD_MEMTYPE_DDR3) {
			printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
			return 1;
		}
	} else {
		memset(pdimm, 0, sizeof(dimm_params_t));
		return 1;
	}

	retval = ddr3_spd_check(spd);
	if (retval) {
		printf("DIMM %u: failed checksum\n", dimm_number);
		return 2;
	}

	/*
	 * The part name in ASCII in the SPD EEPROM is not null terminated.
	 * Guarantee null termination here by presetting all bytes to 0
	 * and copying the part name in ASCII from the SPD onto it
	 */
	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	if ((spd->info_size_crc & 0xF) > 1)
		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);

	/* DIMM organization parameters */
	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
	pdimm->rank_density = compute_ranksize(spd);
	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
	if ((spd->bus_width >> 3) & 0x3)
		pdimm->ec_sdram_width = 8;
	else
		pdimm->ec_sdram_width = 0;
	pdimm->data_width = pdimm->primary_sdram_width
			  + pdimm->ec_sdram_width;
	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);

	/* These are the types defined by the JEDEC DDR3 SPD spec */
	pdimm->mirrored_dimm = 0;
	pdimm->registered_dimm = 0;
	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
	case DDR3_SPD_MODULETYPE_RDIMM:
	case DDR3_SPD_MODULETYPE_MINI_RDIMM:
	case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
		/* Registered/buffered DIMMs */
		pdimm->registered_dimm = 1;
		for (i = 0; i < 16; i += 2) {
			u8 rcw = spd->mod_section.registered.rcw[i/2];
			pdimm->rcw[i]   = (rcw >> 0) & 0x0F;
			pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
		}
		break;

	case DDR3_SPD_MODULETYPE_UDIMM:
	case DDR3_SPD_MODULETYPE_SO_DIMM:
	case DDR3_SPD_MODULETYPE_MICRO_DIMM:
	case DDR3_SPD_MODULETYPE_MINI_UDIMM:
	case DDR3_SPD_MODULETYPE_MINI_CDIMM:
	case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
	case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
	case DDR3_SPD_MODULETYPE_LRDIMM:
	case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
	case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
		/* Unbuffered DIMMs */
		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
			pdimm->mirrored_dimm = 1;
		break;

	default:
		printf("unknown module_type 0x%02X\n", spd->module_type);
		return 1;
	}

	/* SDRAM device parameters */
	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);

	/*
	 * The SPD spec has not the ECC bit,
	 * We consider the DIMM as ECC capability
	 * when the extension bus exist
	 */
	if (pdimm->ec_sdram_width)
		pdimm->edc_config = 0x02;
	else
		pdimm->edc_config = 0x00;

	/*
	 * The SPD spec has not the burst length byte
	 * but DDR3 spec has nature BL8 and BC4,
	 * BL8 -bit3, BC4 -bit2
	 */
	pdimm->burst_lengths_bitmask = 0x0c;

	/* MTB - medium timebase
	 * The unit in the SPD spec is ns,
	 * We convert it to ps.
	 * eg: MTB = 0.125ns (125ps)
	 */
	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
	pdimm->mtb_ps = mtb_ps;

	/*
	 * FTB - fine timebase
	 * use 1/10th of ps as our unit to avoid floating point
	 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
	 */
	ftb_10th_ps =
		((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
	pdimm->ftb_10th_ps = ftb_10th_ps;
	/*
	 * sdram minimum cycle time
	 * we assume the MTB is 0.125ns
	 * eg:
	 * tck_min=15 MTB (1.875ns) ->DDR3-1066
	 *        =12 MTB (1.5ns) ->DDR3-1333
	 *        =10 MTB (1.25ns) ->DDR3-1600
	 */
	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
		(spd->fine_tck_min * ftb_10th_ps) / 10;

	/*
	 * CAS latency supported
	 * bit4 - CL4
	 * bit5 - CL5
	 * bit18 - CL18
	 */
	pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;

	/*
	 * min CAS latency time
	 * eg: taa_min =
	 * DDR3-800D	100 MTB (12.5ns)
	 * DDR3-1066F	105 MTB (13.125ns)
	 * DDR3-1333H	108 MTB (13.5ns)
	 * DDR3-1600H	90 MTB (11.25ns)
	 */
	pdimm->taa_ps = spd->taa_min * mtb_ps +
		(spd->fine_taa_min * ftb_10th_ps) / 10;

	/*
	 * min write recovery time
	 * eg:
	 * twr_min = 120 MTB (15ns) -> all speed grades.
	 */
	pdimm->twr_ps = spd->twr_min * mtb_ps;

	/*
	 * min RAS to CAS delay time
	 * eg: trcd_min =
	 * DDR3-800	100 MTB (12.5ns)
	 * DDR3-1066F	105 MTB (13.125ns)
	 * DDR3-1333H	108 MTB (13.5ns)
	 * DDR3-1600H	90 MTB (11.25)
	 */
	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
		(spd->fine_trcd_min * ftb_10th_ps) / 10;

	/*
	 * min row active to row active delay time
	 * eg: trrd_min =
	 * DDR3-800(1KB page)	80 MTB (10ns)
	 * DDR3-1333(1KB page)	48 MTB (6ns)
	 */
	pdimm->trrd_ps = spd->trrd_min * mtb_ps;

	/*
	 * min row precharge delay time
	 * eg: trp_min =
	 * DDR3-800D	100 MTB (12.5ns)
	 * DDR3-1066F	105 MTB (13.125ns)
	 * DDR3-1333H	108 MTB (13.5ns)
	 * DDR3-1600H	90 MTB (11.25ns)
	 */
	pdimm->trp_ps = spd->trp_min * mtb_ps +
		(spd->fine_trp_min * ftb_10th_ps) / 10;

	/* min active to precharge delay time
	 * eg: tRAS_min =
	 * DDR3-800D	300 MTB (37.5ns)
	 * DDR3-1066F	300 MTB (37.5ns)
	 * DDR3-1333H	288 MTB (36ns)
	 * DDR3-1600H	280 MTB (35ns)
	 */
	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
			* mtb_ps;
	/*
	 * min active to actice/refresh delay time
	 * eg: tRC_min =
	 * DDR3-800D	400 MTB (50ns)
	 * DDR3-1066F	405 MTB (50.625ns)
	 * DDR3-1333H	396 MTB (49.5ns)
	 * DDR3-1600H	370 MTB (46.25ns)
	 */
	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
			* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
	/*
	 * min refresh recovery delay time
	 * eg: tRFC_min =
	 * 512Mb	720 MTB (90ns)
	 * 1Gb		880 MTB (110ns)
	 * 2Gb		1280 MTB (160ns)
	 */
	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
			* mtb_ps;
	/*
	 * min internal write to read command delay time
	 * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
	 * tWRT is at least 4 mclk independent of operating freq.
	 */
	pdimm->twtr_ps = spd->twtr_min * mtb_ps;

	/*
	 * min internal read to precharge command delay time
	 * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
	 * tRTP is at least 4 mclk independent of operating freq.
	 */
	pdimm->trtp_ps = spd->trtp_min * mtb_ps;

	/*
	 * Average periodic refresh interval
	 * tREFI = 7.8 us at normal temperature range
	 *       = 3.9 us at ext temperature range
	 */
	pdimm->refresh_rate_ps = 7800000;
	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
		pdimm->refresh_rate_ps = 3900000;
		pdimm->extended_op_srt = 1;
	}

	/*
	 * min four active window delay time
	 * eg: tfaw_min =
	 * DDR3-800(1KB page)	320 MTB (40ns)
	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
	 * DDR3-1333(1KB page)	240 MTB (30ns)
	 * DDR3-1600(1KB page)	240 MTB (30ns)
	 */
	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
			* mtb_ps;

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
c360ceac	2	/*
73b5396b	3	* Copyright 2008-2012 Freescale Semiconductor, Inc.
c360ceac DL	4	* Dave Liu <daveliu@freescale.com>
	5	*
	6	* calculate the organization and timing parameter
	7	* from ddr3 spd, please refer to the spec
	8	* JEDEC standard No.21-C 4_01_02_11R18.pdf
c360ceac DL	9	*/
	10
	11	#include <common.h>
5614e71b	12	#include <fsl_ddr_sdram.h>
c360ceac	13
5614e71b	14	#include <fsl_ddr.h>
c360ceac DL	15
	16	/*
	17	* Calculate the Density of each Physical Rank.
	18	* Returned size is in bytes.
	19	*
	20	* each rank size =
	21	* sdram capacity(bit) / 8 * primary bus width / sdram width
	22	*
	23	* where: sdram capacity = spd byte4[3:0]
	24	* primary bus width = spd byte8[2:0]
	25	* sdram width = spd byte7[2:0]
	26	*
	27	* SPD byte4 - sdram density and banks
	28	* bit[3:0] size(bit) size(byte)
	29	* 0000 256Mb 32MB
	30	* 0001 512Mb 64MB
	31	* 0010 1Gb 128MB
	32	* 0011 2Gb 256MB
	33	* 0100 4Gb 512MB
	34	* 0101 8Gb 1GB
	35	* 0110 16Gb 2GB
	36	*
	37	* SPD byte8 - module memory bus width
	38	* bit[2:0] primary bus width
	39	* 000 8bits
	40	* 001 16bits
	41	* 010 32bits
	42	* 011 64bits
	43	*
	44	* SPD byte7 - module organiztion
	45	* bit[2:0] sdram device width
	46	* 000 4bits
	47	* 001 8bits
	48	* 010 16bits
	49	* 011 32bits
	50	*
	51	*/
e7563aff	52	static unsigned long long
c360ceac DL	53	compute_ranksize(const ddr3_spd_eeprom_t *spd)
c360ceac DL	54	{
e7563aff	55	unsigned long long bsize;
c360ceac DL	56
	57	int nbit_sdram_cap_bsize = 0;
	58	int nbit_primary_bus_width = 0;
	59	int nbit_sdram_width = 0;
	60
	61	if ((spd->density_banks & 0xf) < 7)
	62	nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
	63	if ((spd->bus_width & 0x7) < 4)
	64	nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
	65	if ((spd->organization & 0x7) < 4)
	66	nbit_sdram_width = (spd->organization & 0x7) + 2;
	67
e66f38da	68	bsize = 1ULL << (nbit_sdram_cap_bsize - 3
c360ceac DL	69	+ nbit_primary_bus_width - nbit_sdram_width);
c360ceac DL	70
cd84b1fa	71	debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
c360ceac DL	72
	73	return bsize;
	74	}
	75
	76	/*
	77	* ddr_compute_dimm_parameters for DDR3 SPD
	78	*
	79	* Compute DIMM parameters based upon the SPD information in spd.
	80	* Writes the results to the dimm_params_t structure pointed by pdimm.
	81	*
	82	*/
03e664d8 YS	83	unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
	84	const ddr3_spd_eeprom_t *spd,
	85	dimm_params_t *pdimm,
	86	unsigned int dimm_number)
c360ceac DL	87	{
	88	unsigned int retval;
	89	unsigned int mtb_ps;
73b5396b	90	int ftb_10th_ps;
9490ff48	91	int i;
c360ceac DL	92
	93	if (spd->mem_type) {
	94	if (spd->mem_type != SPD_MEMTYPE_DDR3) {
	95	printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
	96	return 1;
	97	}
	98	} else {
	99	memset(pdimm, 0, sizeof(dimm_params_t));
	100	return 1;
	101	}
	102
	103	retval = ddr3_spd_check(spd);
	104	if (retval) {
	105	printf("DIMM %u: failed checksum\n", dimm_number);
	106	return 2;
	107	}
	108
	109	/*
	110	* The part name in ASCII in the SPD EEPROM is not null terminated.
	111	* Guarantee null termination here by presetting all bytes to 0
	112	* and copying the part name in ASCII from the SPD onto it
	113	*/
	114	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
d2246549 YS	115	if ((spd->info_size_crc & 0xF) > 1)
d2246549 YS	116	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
c360ceac DL	117
	118	/* DIMM organization parameters */
	119	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
	120	pdimm->rank_density = compute_ranksize(spd);
	121	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	122	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
	123	if ((spd->bus_width >> 3) & 0x3)
	124	pdimm->ec_sdram_width = 8;
	125	else
	126	pdimm->ec_sdram_width = 0;
	127	pdimm->data_width = pdimm->primary_sdram_width
	128	+ pdimm->ec_sdram_width;
b61e0615	129	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
c360ceac	130
c7fd27cc KM	131	/* These are the types defined by the JEDEC DDR3 SPD spec */
	132	pdimm->mirrored_dimm = 0;
	133	pdimm->registered_dimm = 0;
	134	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
	135	case DDR3_SPD_MODULETYPE_RDIMM:
	136	case DDR3_SPD_MODULETYPE_MINI_RDIMM:
2f3a71f2	137	case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
c7fd27cc KM	138	/* Registered/buffered DIMMs */
c7fd27cc KM	139	pdimm->registered_dimm = 1;
9490ff48	140	for (i = 0; i < 16; i += 2) {
c7fd27cc KM	141	u8 rcw = spd->mod_section.registered.rcw[i/2];
	142	pdimm->rcw[i] = (rcw >> 0) & 0x0F;
	143	pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
9490ff48	144	}
c360ceac	145	break;
c7fd27cc KM	146
	147	case DDR3_SPD_MODULETYPE_UDIMM:
	148	case DDR3_SPD_MODULETYPE_SO_DIMM:
	149	case DDR3_SPD_MODULETYPE_MICRO_DIMM:
	150	case DDR3_SPD_MODULETYPE_MINI_UDIMM:
2f3a71f2 IS	151	case DDR3_SPD_MODULETYPE_MINI_CDIMM:
	152	case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
	153	case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
	154	case DDR3_SPD_MODULETYPE_LRDIMM:
	155	case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
	156	case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
c7fd27cc KM	157	/* Unbuffered DIMMs */
	158	if (spd->mod_section.unbuffered.addr_mapping & 0x1)
	159	pdimm->mirrored_dimm = 1;
c360ceac DL	160	break;
	161
	162	default:
c7fd27cc	163	printf("unknown module_type 0x%02X\n", spd->module_type);
c360ceac DL	164	return 1;
	165	}
	166
	167	/* SDRAM device parameters */
	168	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
	169	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
	170	pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
	171
	172	/*
	173	* The SPD spec has not the ECC bit,
	174	* We consider the DIMM as ECC capability
	175	* when the extension bus exist
	176	*/
	177	if (pdimm->ec_sdram_width)
	178	pdimm->edc_config = 0x02;
	179	else
	180	pdimm->edc_config = 0x00;
	181
	182	/*
	183	* The SPD spec has not the burst length byte
	184	* but DDR3 spec has nature BL8 and BC4,
	185	* BL8 -bit3, BC4 -bit2
	186	*/
	187	pdimm->burst_lengths_bitmask = 0x0c;
c360ceac DL	188
	189	/* MTB - medium timebase
	190	* The unit in the SPD spec is ns,
	191	* We convert it to ps.
	192	* eg: MTB = 0.125ns (125ps)
	193	*/
	194	mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
	195	pdimm->mtb_ps = mtb_ps;
	196
73b5396b YS	197	/*
	198	* FTB - fine timebase
	199	* use 1/10th of ps as our unit to avoid floating point
	200	* eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
	201	*/
	202	ftb_10th_ps =
	203	((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
	204	pdimm->ftb_10th_ps = ftb_10th_ps;
c360ceac DL	205	/*
	206	* sdram minimum cycle time
	207	* we assume the MTB is 0.125ns
	208	* eg:
0dd38a35	209	* tck_min=15 MTB (1.875ns) ->DDR3-1066
c360ceac DL	210	* =12 MTB (1.5ns) ->DDR3-1333
	211	* =10 MTB (1.25ns) ->DDR3-1600
	212	*/
0dd38a35 PJ	213	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
0dd38a35 PJ	214	(spd->fine_tck_min * ftb_10th_ps) / 10;
c360ceac DL	215
	216	/*
	217	* CAS latency supported
	218	* bit4 - CL4
	219	* bit5 - CL5
	220	* bit18 - CL18
	221	*/
0dd38a35	222	pdimm->caslat_x = ((spd->caslat_msb << 8) \| spd->caslat_lsb) << 4;
c360ceac DL	223
	224	/*
	225	* min CAS latency time
0dd38a35	226	* eg: taa_min =
c360ceac DL	227	* DDR3-800D 100 MTB (12.5ns)
	228	* DDR3-1066F 105 MTB (13.125ns)
	229	* DDR3-1333H 108 MTB (13.5ns)
	230	* DDR3-1600H 90 MTB (11.25ns)
	231	*/
0dd38a35 PJ	232	pdimm->taa_ps = spd->taa_min * mtb_ps +
0dd38a35 PJ	233	(spd->fine_taa_min * ftb_10th_ps) / 10;
c360ceac DL	234
	235	/*
	236	* min write recovery time
	237	* eg:
0dd38a35	238	* twr_min = 120 MTB (15ns) -> all speed grades.
c360ceac	239	*/
0dd38a35	240	pdimm->twr_ps = spd->twr_min * mtb_ps;
c360ceac DL	241
	242	/*
	243	* min RAS to CAS delay time
0dd38a35	244	* eg: trcd_min =
c360ceac DL	245	* DDR3-800 100 MTB (12.5ns)
	246	* DDR3-1066F 105 MTB (13.125ns)
	247	* DDR3-1333H 108 MTB (13.5ns)
	248	* DDR3-1600H 90 MTB (11.25)
	249	*/
0dd38a35 PJ	250	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
0dd38a35 PJ	251	(spd->fine_trcd_min * ftb_10th_ps) / 10;
c360ceac DL	252
	253	/*
	254	* min row active to row active delay time
0dd38a35	255	* eg: trrd_min =
c360ceac DL	256	* DDR3-800(1KB page) 80 MTB (10ns)
	257	* DDR3-1333(1KB page) 48 MTB (6ns)
	258	*/
0dd38a35	259	pdimm->trrd_ps = spd->trrd_min * mtb_ps;
c360ceac DL	260
	261	/*
	262	* min row precharge delay time
0dd38a35	263	* eg: trp_min =
c360ceac DL	264	* DDR3-800D 100 MTB (12.5ns)
	265	* DDR3-1066F 105 MTB (13.125ns)
	266	* DDR3-1333H 108 MTB (13.5ns)
	267	* DDR3-1600H 90 MTB (11.25ns)
	268	*/
0dd38a35 PJ	269	pdimm->trp_ps = spd->trp_min * mtb_ps +
0dd38a35 PJ	270	(spd->fine_trp_min * ftb_10th_ps) / 10;
c360ceac DL	271
	272	/* min active to precharge delay time
	273	* eg: tRAS_min =
	274	* DDR3-800D 300 MTB (37.5ns)
	275	* DDR3-1066F 300 MTB (37.5ns)
	276	* DDR3-1333H 288 MTB (36ns)
	277	* DDR3-1600H 280 MTB (35ns)
	278	*/
0dd38a35	279	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) \| spd->tras_min_lsb)
c360ceac DL	280	* mtb_ps;
	281	/*
	282	* min active to actice/refresh delay time
	283	* eg: tRC_min =
	284	* DDR3-800D 400 MTB (50ns)
	285	* DDR3-1066F 405 MTB (50.625ns)
	286	* DDR3-1333H 396 MTB (49.5ns)
	287	* DDR3-1600H 370 MTB (46.25ns)
	288	*/
0dd38a35 PJ	289	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) \| spd->trc_min_lsb)
0dd38a35 PJ	290	* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
c360ceac DL	291	/*
	292	* min refresh recovery delay time
	293	* eg: tRFC_min =
	294	* 512Mb 720 MTB (90ns)
	295	* 1Gb 880 MTB (110ns)
	296	* 2Gb 1280 MTB (160ns)
	297	*/
0dd38a35	298	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) \| spd->trfc_min_lsb)
c360ceac DL	299	* mtb_ps;
	300	/*
	301	* min internal write to read command delay time
0dd38a35	302	* eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
c360ceac DL	303	* tWRT is at least 4 mclk independent of operating freq.
c360ceac DL	304	*/
0dd38a35	305	pdimm->twtr_ps = spd->twtr_min * mtb_ps;
c360ceac DL	306
	307	/*
	308	* min internal read to precharge command delay time
0dd38a35	309	* eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
c360ceac DL	310	* tRTP is at least 4 mclk independent of operating freq.
c360ceac DL	311	*/
0dd38a35	312	pdimm->trtp_ps = spd->trtp_min * mtb_ps;
c360ceac DL	313
	314	/*
	315	* Average periodic refresh interval
	316	* tREFI = 7.8 us at normal temperature range
	317	* = 3.9 us at ext temperature range
	318	*/
	319	pdimm->refresh_rate_ps = 7800000;
7e157b0a VL	320	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
	321	pdimm->refresh_rate_ps = 3900000;
	322	pdimm->extended_op_srt = 1;
	323	}
c360ceac DL	324
	325	/*
	326	* min four active window delay time
0dd38a35	327	* eg: tfaw_min =
c360ceac DL	328	* DDR3-800(1KB page) 320 MTB (40ns)
	329	* DDR3-1066(1KB page) 300 MTB (37.5ns)
	330	* DDR3-1333(1KB page) 240 MTB (30ns)
	331	* DDR3-1600(1KB page) 240 MTB (30ns)
	332	*/
0dd38a35	333	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) \| spd->tfaw_min)
c360ceac DL	334	* mtb_ps;
c360ceac DL	335
c360ceac DL	336	return 0;
c360ceac DL	337	}