[thirdparty/u-boot.git] / drivers / mmc / sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2011, Marvell Semiconductor Inc.
 * Lei Wen <leiwen@marvell.com>
 *
 * Back ported to the 8xx platform (from the 8260 platform) by
 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
#else
void *aligned_buffer;
#endif

static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
	unsigned long timeout;

	/* Wait max 100 ms */
	timeout = 100;
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
		if (timeout == 0) {
			printf("%s: Reset 0x%x never completed.\n",
			       __func__, (int)mask);
			return;
		}
		timeout--;
		udelay(1000);
	}
}

static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
	int i;
	if (cmd->resp_type & MMC_RSP_136) {
		/* CRC is stripped so we need to do some shifting. */
		for (i = 0; i < 4; i++) {
			cmd->response[i] = sdhci_readl(host,
					SDHCI_RESPONSE + (3-i)*4) << 8;
			if (i != 3)
				cmd->response[i] |= sdhci_readb(host,
						SDHCI_RESPONSE + (3-i)*4-1);
		}
	} else {
		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	}
}

static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
	int i;
	char *offs;
	for (i = 0; i < data->blocksize; i += 4) {
		offs = data->dest + i;
		if (data->flags == MMC_DATA_READ)
			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
		else
			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
	}
}

static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
				unsigned int start_addr)
{
	unsigned int stat, rdy, mask, timeout, block = 0;
	bool transfer_done = false;
#ifdef CONFIG_MMC_SDHCI_SDMA
	unsigned char ctrl;
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	ctrl &= ~SDHCI_CTRL_DMA_MASK;
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
#endif

	timeout = 1000000;
	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR) {
			pr_debug("%s: Error detected in status(0x%X)!\n",
				 __func__, stat);
			return -EIO;
		}
		if (!transfer_done && (stat & rdy)) {
			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
				continue;
			sdhci_writel(host, rdy, SDHCI_INT_STATUS);
			sdhci_transfer_pio(host, data);
			data->dest += data->blocksize;
			if (++block >= data->blocks) {
				/* Keep looping until the SDHCI_INT_DATA_END is
				 * cleared, even if we finished sending all the
				 * blocks.
				 */
				transfer_done = true;
				continue;
			}
		}
#ifdef CONFIG_MMC_SDHCI_SDMA
		if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		}
#endif
		if (timeout-- > 0)
			udelay(10);
		else {
			printf("%s: Transfer data timeout\n", __func__);
			return -ETIMEDOUT;
		}
	} while (!(stat & SDHCI_INT_DATA_END));
	return 0;
}

/*
 * No command will be sent by driver if card is busy, so driver must wait
 * for card ready state.
 * Every time when card is busy after timeout then (last) timeout value will be
 * increased twice but only if it doesn't exceed global defined maximum.
 * Each function call will use last timeout value.
 */
#define SDHCI_CMD_MAX_TIMEOUT			3200
#define SDHCI_CMD_DEFAULT_TIMEOUT		100
#define SDHCI_READ_STATUS_TIMEOUT		1000

#ifdef CONFIG_DM_MMC
static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

#else
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
#endif
	struct sdhci_host *host = mmc->priv;
	unsigned int stat = 0;
	int ret = 0;
	int trans_bytes = 0, is_aligned = 1;
	u32 mask, flags, mode;
	unsigned int time = 0, start_addr = 0;
	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
	unsigned start = get_timer(0);

	/* Timeout unit - ms */
	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;

	mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		mask &= ~SDHCI_DATA_INHIBIT;

	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
		if (time >= cmd_timeout) {
			printf("%s: MMC: %d busy ", __func__, mmc_dev);
			if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
				cmd_timeout += cmd_timeout;
				printf("timeout increasing to: %u ms.\n",
				       cmd_timeout);
			} else {
				puts("timeout.\n");
				return -ECOMM;
			}
		}
		time++;
		udelay(1000);
	}

	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);

	mask = SDHCI_INT_RESPONSE;
	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->resp_type & MMC_RSP_BUSY) {
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
		if (data)
			mask |= SDHCI_INT_DATA_END;
	} else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
	if (data)
		flags |= SDHCI_CMD_DATA;

	/* Set Transfer mode regarding to data flag */
	if (data) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
		mode = SDHCI_TRNS_BLK_CNT_EN;
		trans_bytes = data->blocks * data->blocksize;
		if (data->blocks > 1)
			mode |= SDHCI_TRNS_MULTI;

		if (data->flags == MMC_DATA_READ)
			mode |= SDHCI_TRNS_READ;

#ifdef CONFIG_MMC_SDHCI_SDMA
		if (data->flags == MMC_DATA_READ)
			start_addr = (unsigned long)data->dest;
		else
			start_addr = (unsigned long)data->src;
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				(start_addr & 0x7) != 0x0) {
			is_aligned = 0;
			start_addr = (unsigned long)aligned_buffer;
			if (data->flags != MMC_DATA_READ)
				memcpy(aligned_buffer, data->src, trans_bytes);
		}

#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
		/*
		 * Always use this bounce-buffer when
		 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
		 */
		is_aligned = 0;
		start_addr = (unsigned long)aligned_buffer;
		if (data->flags != MMC_DATA_READ)
			memcpy(aligned_buffer, data->src, trans_bytes);
#endif

		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
		mode |= SDHCI_TRNS_DMA;
#endif
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
				data->blocksize),
				SDHCI_BLOCK_SIZE);
		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
	} else if (cmd->resp_type & MMC_RSP_BUSY) {
		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	}

	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDHCI_SDMA
	if (data) {
		trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
		flush_cache(start_addr, trans_bytes);
	}
#endif
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
	start = get_timer(0);
	do {
		stat = sdhci_readl(host, SDHCI_INT_STATUS);
		if (stat & SDHCI_INT_ERROR)
			break;

		if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
				return 0;
			} else {
				printf("%s: Timeout for status update!\n",
				       __func__);
				return -ETIMEDOUT;
			}
		}
	} while ((stat & mask) != mask);

	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
		sdhci_cmd_done(host, cmd);
		sdhci_writel(host, mask, SDHCI_INT_STATUS);
	} else
		ret = -1;

	if (!ret && data)
		ret = sdhci_transfer_data(host, data, start_addr);

	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
		udelay(1000);

	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	if (!ret) {
		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
				!is_aligned && (data->flags == MMC_DATA_READ))
			memcpy(data->dest, aligned_buffer, trans_bytes);
		return 0;
	}

	sdhci_reset(host, SDHCI_RESET_CMD);
	sdhci_reset(host, SDHCI_RESET_DATA);
	if (stat & SDHCI_INT_TIMEOUT)
		return -ETIMEDOUT;
	else
		return -ECOMM;
}

static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
	struct sdhci_host *host = mmc->priv;
	unsigned int div, clk = 0, timeout;

	/* Wait max 20 ms */
	timeout = 200;
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
			   (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
		if (timeout == 0) {
			printf("%s: Timeout to wait cmd & data inhibit\n",
			       __func__);
			return -EBUSY;
		}

		timeout--;
		udelay(100);
	}

	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return 0;

	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
			for (div = 1; div <= 1024; div++) {
				if ((host->max_clk / div) <= clock)
					break;
			}

			/*
			 * Set Programmable Clock Mode in the Clock
			 * Control register.
			 */
			clk = SDHCI_PROG_CLOCK_MODE;
			div--;
		} else {
			/* Version 3.00 divisors must be a multiple of 2. */
			if (host->max_clk <= clock) {
				div = 1;
			} else {
				for (div = 2;
				     div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((host->max_clk / div) <= clock)
						break;
				}
			}
			div >>= 1;
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
			if ((host->max_clk / div) <= clock)
				break;
		}
		div >>= 1;
	}

	if (host->ops && host->ops->set_clock)
		host->ops->set_clock(host, div);

	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			printf("%s: Internal clock never stabilised.\n",
			       __func__);
			return -EBUSY;
		}
		timeout--;
		udelay(1000);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	return 0;
}

static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
	u8 pwr = 0;

	if (power != (unsigned short)-1) {
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		}
	}

	if (pwr == 0) {
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
		return;
	}

	pwr |= SDHCI_POWER_ON;

	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}

#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int sdhci_set_ios(struct mmc *mmc)
{
#endif
	u32 ctrl;
	struct sdhci_host *host = mmc->priv;

	if (host->ops && host->ops->set_control_reg)
		host->ops->set_control_reg(host);

	if (mmc->clock != host->clock)
		sdhci_set_clock(mmc, mmc->clock);

	/* Set bus width */
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if (mmc->bus_width == 8) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
			ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (mmc->bus_width == 4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}

	if (mmc->clock > 26000000)
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

	if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
	    (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
		ctrl &= ~SDHCI_CTRL_HISPD;

	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

	/* If available, call the driver specific "post" set_ios() function */
	if (host->ops && host->ops->set_ios_post)
		host->ops->set_ios_post(host);

	return 0;
}

static int sdhci_init(struct mmc *mmc)
{
	struct sdhci_host *host = mmc->priv;

	sdhci_reset(host, SDHCI_RESET_ALL);

	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
		aligned_buffer = memalign(8, 512*1024);
		if (!aligned_buffer) {
			printf("%s: Aligned buffer alloc failed!!!\n",
			       __func__);
			return -ENOMEM;
		}
	}

	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);

	if (host->ops && host->ops->get_cd)
		host->ops->get_cd(host);

	/* Enable only interrupts served by the SD controller */
	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
		     SDHCI_INT_ENABLE);
	/* Mask all sdhci interrupt sources */
	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);

	return 0;
}

#ifdef CONFIG_DM_MMC
int sdhci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return sdhci_init(mmc);
}

const struct dm_mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
};
#else
static const struct mmc_ops sdhci_ops = {
	.send_cmd	= sdhci_send_command,
	.set_ios	= sdhci_set_ios,
	.init		= sdhci_init,
};
#endif

int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
		u32 f_max, u32 f_min)
{
	u32 caps, caps_1;

	caps = sdhci_readl(host, SDHCI_CAPABILITIES);

#ifdef CONFIG_MMC_SDHCI_SDMA
	if (!(caps & SDHCI_CAN_DO_SDMA)) {
		printf("%s: Your controller doesn't support SDMA!!\n",
		       __func__);
		return -EINVAL;
	}
#endif
	if (host->quirks & SDHCI_QUIRK_REG32_RW)
		host->version =
			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	else
		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);

	cfg->name = host->name;
#ifndef CONFIG_DM_MMC
	cfg->ops = &sdhci_ops;
#endif

	/* Check whether the clock multiplier is supported or not */
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
				SDHCI_CLOCK_MUL_SHIFT;
	}

	if (host->max_clk == 0) {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		else
			host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
				SDHCI_CLOCK_BASE_SHIFT;
		host->max_clk *= 1000000;
		if (host->clk_mul)
			host->max_clk *= host->clk_mul;
	}
	if (host->max_clk == 0) {
		printf("%s: Hardware doesn't specify base clock frequency\n",
		       __func__);
		return -EINVAL;
	}
	if (f_max && (f_max < host->max_clk))
		cfg->f_max = f_max;
	else
		cfg->f_max = host->max_clk;
	if (f_min)
		cfg->f_min = f_min;
	else {
		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
		else
			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
	}
	cfg->voltages = 0;
	if (caps & SDHCI_CAN_VDD_330)
		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
	if (caps & SDHCI_CAN_VDD_300)
		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & SDHCI_CAN_VDD_180)
		cfg->voltages |= MMC_VDD_165_195;

	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
		cfg->voltages |= host->voltages;

	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;

	/* Since Host Controller Version3.0 */
	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
		if (!(caps & SDHCI_CAN_DO_8BIT))
			cfg->host_caps &= ~MMC_MODE_8BIT;
	}

	if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
		cfg->host_caps &= ~MMC_MODE_HS;
		cfg->host_caps &= ~MMC_MODE_HS_52MHz;
	}

	if (host->host_caps)
		cfg->host_caps |= host->host_caps;

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	return 0;
}

#ifdef CONFIG_BLK
int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
{
	int ret;

	ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
	if (ret)
		return ret;

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL) {
		printf("%s: mmc create fail!\n", __func__);
		return -ENOMEM;
	}

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
af62a557 LW	2	/*
	3	* Copyright 2011, Marvell Semiconductor Inc.
	4	* Lei Wen <leiwen@marvell.com>
	5	*
af62a557 LW	6	* Back ported to the 8xx platform (from the 8260 platform) by
	7	* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
	8	*/
	9
	10	#include <common.h>
2a809093	11	#include <errno.h>
af62a557 LW	12	#include <malloc.h>
	13	#include <mmc.h>
	14	#include <sdhci.h>
	15
492d3223 SR	16	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	17	void aligned_buffer = (void )CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
	18	#else
af62a557	19	void *aligned_buffer;
492d3223	20	#endif
af62a557 LW	21
	22	static void sdhci_reset(struct sdhci_host *host, u8 mask)
	23	{
	24	unsigned long timeout;
	25
	26	/* Wait max 100 ms */
	27	timeout = 100;
	28	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
	29	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
	30	if (timeout == 0) {
30e6d979 DR	31	printf("%s: Reset 0x%x never completed.\n",
30e6d979 DR	32	__func__, (int)mask);
af62a557 LW	33	return;
	34	}
	35	timeout--;
	36	udelay(1000);
	37	}
	38	}
	39
	40	static void sdhci_cmd_done(struct sdhci_host host, struct mmc_cmd cmd)
	41	{
	42	int i;
	43	if (cmd->resp_type & MMC_RSP_136) {
	44	/* CRC is stripped so we need to do some shifting. */
	45	for (i = 0; i < 4; i++) {
	46	cmd->response[i] = sdhci_readl(host,
	47	SDHCI_RESPONSE + (3-i)*4) << 8;
	48	if (i != 3)
	49	cmd->response[i] \|= sdhci_readb(host,
	50	SDHCI_RESPONSE + (3-i)*4-1);
	51	}
	52	} else {
	53	cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
	54	}
	55	}
	56
	57	static void sdhci_transfer_pio(struct sdhci_host host, struct mmc_data data)
	58	{
	59	int i;
	60	char *offs;
	61	for (i = 0; i < data->blocksize; i += 4) {
	62	offs = data->dest + i;
	63	if (data->flags == MMC_DATA_READ)
	64	(u32 )offs = sdhci_readl(host, SDHCI_BUFFER);
	65	else
	66	sdhci_writel(host, (u32 )offs, SDHCI_BUFFER);
	67	}
	68	}
	69
	70	static int sdhci_transfer_data(struct sdhci_host host, struct mmc_data data,
	71	unsigned int start_addr)
	72	{
a004abde	73	unsigned int stat, rdy, mask, timeout, block = 0;
7dde50d7	74	bool transfer_done = false;
45a68fe2	75	#ifdef CONFIG_MMC_SDHCI_SDMA
804c7f42	76	unsigned char ctrl;
2c011847	77	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42	78	ctrl &= ~SDHCI_CTRL_DMA_MASK;
2c011847	79	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
804c7f42	80	#endif
af62a557	81
5d48e422	82	timeout = 1000000;
af62a557 LW	83	rdy = SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_AVAIL;
	84	mask = SDHCI_DATA_AVAILABLE \| SDHCI_SPACE_AVAILABLE;
	85	do {
	86	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	87	if (stat & SDHCI_INT_ERROR) {
61f2e5ee MY	88	pr_debug("%s: Error detected in status(0x%X)!\n",
61f2e5ee MY	89	__func__, stat);
2cb5d67c	90	return -EIO;
af62a557	91	}
7dde50d7	92	if (!transfer_done && (stat & rdy)) {
af62a557 LW	93	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
	94	continue;
	95	sdhci_writel(host, rdy, SDHCI_INT_STATUS);
	96	sdhci_transfer_pio(host, data);
	97	data->dest += data->blocksize;
7dde50d7 AD	98	if (++block >= data->blocks) {
	99	/* Keep looping until the SDHCI_INT_DATA_END is
	100	* cleared, even if we finished sending all the
	101	* blocks.
	102	*/
	103	transfer_done = true;
	104	continue;
	105	}
af62a557	106	}
45a68fe2	107	#ifdef CONFIG_MMC_SDHCI_SDMA
7dde50d7	108	if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
af62a557	109	sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
3e81c772	110	start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
af62a557 LW	111	start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
	112	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	113	}
	114	#endif
a004abde LW	115	if (timeout-- > 0)
	116	udelay(10);
	117	else {
30e6d979	118	printf("%s: Transfer data timeout\n", __func__);
2cb5d67c	119	return -ETIMEDOUT;
a004abde	120	}
af62a557 LW	121	} while (!(stat & SDHCI_INT_DATA_END));
	122	return 0;
	123	}
	124
56b34bc6 PM	125	/*
	126	* No command will be sent by driver if card is busy, so driver must wait
	127	* for card ready state.
	128	* Every time when card is busy after timeout then (last) timeout value will be
	129	* increased twice but only if it doesn't exceed global defined maximum.
65a25b20	130	* Each function call will use last timeout value.
56b34bc6	131	*/
65a25b20	132	#define SDHCI_CMD_MAX_TIMEOUT 3200
d8ce77b2	133	#define SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439	134	#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6	135
e7881d85	136	#ifdef CONFIG_DM_MMC
ef1e4eda SG	137	static int sdhci_send_command(struct udevice dev, struct mmc_cmd cmd,
	138	struct mmc_data *data)
	139	{
	140	struct mmc *mmc = mmc_get_mmc_dev(dev);
	141
	142	#else
6588c78b	143	static int sdhci_send_command(struct mmc mmc, struct mmc_cmd cmd,
ef1e4eda	144	struct mmc_data *data)
af62a557	145	{
ef1e4eda	146	#endif
93bfd616	147	struct sdhci_host *host = mmc->priv;
af62a557 LW	148	unsigned int stat = 0;
	149	int ret = 0;
	150	int trans_bytes = 0, is_aligned = 1;
	151	u32 mask, flags, mode;
56b34bc6	152	unsigned int time = 0, start_addr = 0;
19d2e342	153	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
29905a45	154	unsigned start = get_timer(0);
af62a557	155
56b34bc6	156	/* Timeout unit - ms */
d8ce77b2	157	static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557	158
af62a557 LW	159	mask = SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT;
	160
	161	/* We shouldn't wait for data inihibit for stop commands, even
	162	though they might use busy signaling */
	163	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	164	mask &= ~SDHCI_DATA_INHIBIT;
	165
	166	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6	167	if (time >= cmd_timeout) {
30e6d979	168	printf("%s: MMC: %d busy ", __func__, mmc_dev);
65a25b20	169	if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
56b34bc6 PM	170	cmd_timeout += cmd_timeout;
	171	printf("timeout increasing to: %u ms.\n",
	172	cmd_timeout);
	173	} else {
	174	puts("timeout.\n");
915ffa52	175	return -ECOMM;
56b34bc6	176	}
af62a557	177	}
56b34bc6	178	time++;
af62a557 LW	179	udelay(1000);
	180	}
	181
713e6815 JRO	182	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
713e6815 JRO	183
af62a557 LW	184	mask = SDHCI_INT_RESPONSE;
	185	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	186	flags = SDHCI_CMD_RESP_NONE;
	187	else if (cmd->resp_type & MMC_RSP_136)
	188	flags = SDHCI_CMD_RESP_LONG;
	189	else if (cmd->resp_type & MMC_RSP_BUSY) {
	190	flags = SDHCI_CMD_RESP_SHORT_BUSY;
17ea3c86 JC	191	if (data)
17ea3c86 JC	192	mask \|= SDHCI_INT_DATA_END;
af62a557 LW	193	} else
	194	flags = SDHCI_CMD_RESP_SHORT;
	195
	196	if (cmd->resp_type & MMC_RSP_CRC)
	197	flags \|= SDHCI_CMD_CRC;
	198	if (cmd->resp_type & MMC_RSP_OPCODE)
	199	flags \|= SDHCI_CMD_INDEX;
	200	if (data)
	201	flags \|= SDHCI_CMD_DATA;
	202
30e6d979	203	/* Set Transfer mode regarding to data flag */
bb7b4ef3	204	if (data) {
af62a557 LW	205	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
	206	mode = SDHCI_TRNS_BLK_CNT_EN;
	207	trans_bytes = data->blocks * data->blocksize;
	208	if (data->blocks > 1)
	209	mode \|= SDHCI_TRNS_MULTI;
	210
	211	if (data->flags == MMC_DATA_READ)
	212	mode \|= SDHCI_TRNS_READ;
	213
45a68fe2	214	#ifdef CONFIG_MMC_SDHCI_SDMA
af62a557	215	if (data->flags == MMC_DATA_READ)
3c1fcb77	216	start_addr = (unsigned long)data->dest;
af62a557	217	else
3c1fcb77	218	start_addr = (unsigned long)data->src;
af62a557 LW	219	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	220	(start_addr & 0x7) != 0x0) {
	221	is_aligned = 0;
3c1fcb77	222	start_addr = (unsigned long)aligned_buffer;
af62a557 LW	223	if (data->flags != MMC_DATA_READ)
	224	memcpy(aligned_buffer, data->src, trans_bytes);
	225	}
	226
492d3223 SR	227	#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
	228	/*
	229	* Always use this bounce-buffer when
	230	* CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
	231	*/
	232	is_aligned = 0;
	233	start_addr = (unsigned long)aligned_buffer;
	234	if (data->flags != MMC_DATA_READ)
	235	memcpy(aligned_buffer, data->src, trans_bytes);
	236	#endif
	237
af62a557 LW	238	sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
	239	mode \|= SDHCI_TRNS_DMA;
	240	#endif
	241	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
	242	data->blocksize),
	243	SDHCI_BLOCK_SIZE);
	244	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	245	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd KL	246	} else if (cmd->resp_type & MMC_RSP_BUSY) {
5e1c23cd KL	247	sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557 LW	248	}
	249
	250	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
45a68fe2	251	#ifdef CONFIG_MMC_SDHCI_SDMA
bb7b4ef3	252	if (data) {
fa7720b2 KL	253	trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
	254	flush_cache(start_addr, trans_bytes);
	255	}
af62a557 LW	256	#endif
af62a557 LW	257	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45	258	start = get_timer(0);
af62a557 LW	259	do {
	260	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	261	if (stat & SDHCI_INT_ERROR)
	262	break;
af62a557	263
bae4a1fd MY	264	if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
	265	if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
	266	return 0;
	267	} else {
	268	printf("%s: Timeout for status update!\n",
	269	__func__);
915ffa52	270	return -ETIMEDOUT;
bae4a1fd	271	}
3a638320	272	}
bae4a1fd	273	} while ((stat & mask) != mask);
3a638320	274
af62a557 LW	275	if ((stat & (SDHCI_INT_ERROR \| mask)) == mask) {
	276	sdhci_cmd_done(host, cmd);
	277	sdhci_writel(host, mask, SDHCI_INT_STATUS);
	278	} else
	279	ret = -1;
	280
	281	if (!ret && data)
	282	ret = sdhci_transfer_data(host, data, start_addr);
	283
13243f2e TB	284	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
	285	udelay(1000);
	286
af62a557 LW	287	stat = sdhci_readl(host, SDHCI_INT_STATUS);
	288	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
	289	if (!ret) {
	290	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
	291	!is_aligned && (data->flags == MMC_DATA_READ))
	292	memcpy(data->dest, aligned_buffer, trans_bytes);
	293	return 0;
	294	}
	295
	296	sdhci_reset(host, SDHCI_RESET_CMD);
	297	sdhci_reset(host, SDHCI_RESET_DATA);
	298	if (stat & SDHCI_INT_TIMEOUT)
915ffa52	299	return -ETIMEDOUT;
af62a557	300	else
915ffa52	301	return -ECOMM;
af62a557 LW	302	}
	303
	304	static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
	305	{
93bfd616	306	struct sdhci_host *host = mmc->priv;
899fb9e3	307	unsigned int div, clk = 0, timeout;
af62a557	308
79667b7b WY	309	/* Wait max 20 ms */
	310	timeout = 200;
	311	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
	312	(SDHCI_CMD_INHIBIT \| SDHCI_DATA_INHIBIT)) {
	313	if (timeout == 0) {
	314	printf("%s: Timeout to wait cmd & data inhibit\n",
	315	__func__);
2cb5d67c	316	return -EBUSY;
79667b7b WY	317	}
	318
	319	timeout--;
	320	udelay(100);
	321	}
	322
899fb9e3	323	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af62a557 LW	324
	325	if (clock == 0)
	326	return 0;
	327
113e5dfc	328	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
6dffdbc3 WY	329	/*
	330	* Check if the Host Controller supports Programmable Clock
	331	* Mode.
	332	*/
	333	if (host->clk_mul) {
	334	for (div = 1; div <= 1024; div++) {
0e0dcc19	335	if ((host->max_clk / div) <= clock)
af62a557 LW	336	break;
af62a557 LW	337	}
6dffdbc3 WY	338
	339	/*
	340	* Set Programmable Clock Mode in the Clock
	341	* Control register.
	342	*/
	343	clk = SDHCI_PROG_CLOCK_MODE;
	344	div--;
	345	} else {
	346	/* Version 3.00 divisors must be a multiple of 2. */
6d0e34bf	347	if (host->max_clk <= clock) {
6dffdbc3 WY	348	div = 1;
	349	} else {
	350	for (div = 2;
	351	div < SDHCI_MAX_DIV_SPEC_300;
	352	div += 2) {
6d0e34bf	353	if ((host->max_clk / div) <= clock)
6dffdbc3 WY	354	break;
	355	}
	356	}
	357	div >>= 1;
af62a557 LW	358	}
	359	} else {
	360	/* Version 2.00 divisors must be a power of 2. */
	361	for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
6d0e34bf	362	if ((host->max_clk / div) <= clock)
af62a557 LW	363	break;
af62a557 LW	364	}
6dffdbc3	365	div >>= 1;
af62a557	366	}
af62a557	367
bf9c4d14	368	if (host->ops && host->ops->set_clock)
62226b68	369	host->ops->set_clock(host, div);
b09ed6e4	370
6dffdbc3	371	clk \|= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
af62a557 LW	372	clk \|= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
	373	<< SDHCI_DIVIDER_HI_SHIFT;
	374	clk \|= SDHCI_CLOCK_INT_EN;
	375	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	376
	377	/* Wait max 20 ms */
	378	timeout = 20;
	379	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	380	& SDHCI_CLOCK_INT_STABLE)) {
	381	if (timeout == 0) {
30e6d979 DR	382	printf("%s: Internal clock never stabilised.\n",
30e6d979 DR	383	__func__);
2cb5d67c	384	return -EBUSY;
af62a557 LW	385	}
	386	timeout--;
	387	udelay(1000);
	388	}
	389
	390	clk \|= SDHCI_CLOCK_CARD_EN;
	391	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	392	return 0;
	393	}
	394
	395	static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
	396	{
	397	u8 pwr = 0;
	398
	399	if (power != (unsigned short)-1) {
	400	switch (1 << power) {
	401	case MMC_VDD_165_195:
	402	pwr = SDHCI_POWER_180;
	403	break;
	404	case MMC_VDD_29_30:
	405	case MMC_VDD_30_31:
	406	pwr = SDHCI_POWER_300;
	407	break;
	408	case MMC_VDD_32_33:
	409	case MMC_VDD_33_34:
	410	pwr = SDHCI_POWER_330;
	411	break;
	412	}
	413	}
	414
	415	if (pwr == 0) {
	416	sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
	417	return;
	418	}
	419
	420	pwr \|= SDHCI_POWER_ON;
	421
	422	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	423	}
	424
e7881d85	425	#ifdef CONFIG_DM_MMC
ef1e4eda SG	426	static int sdhci_set_ios(struct udevice *dev)
	427	{
	428	struct mmc *mmc = mmc_get_mmc_dev(dev);
	429	#else
07b0b9c0	430	static int sdhci_set_ios(struct mmc *mmc)
af62a557	431	{
ef1e4eda	432	#endif
af62a557	433	u32 ctrl;
93bfd616	434	struct sdhci_host *host = mmc->priv;
af62a557	435
bf9c4d14	436	if (host->ops && host->ops->set_control_reg)
62226b68	437	host->ops->set_control_reg(host);
236bfecf	438
af62a557 LW	439	if (mmc->clock != host->clock)
	440	sdhci_set_clock(mmc, mmc->clock);
	441
	442	/* Set bus width */
	443	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	444	if (mmc->bus_width == 8) {
	445	ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc JC	446	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
113e5dfc JC	447	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	448	ctrl \|= SDHCI_CTRL_8BITBUS;
af62a557 LW	449	} else {
f88a429f MR	450	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) \|\|
f88a429f MR	451	(host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557 LW	452	ctrl &= ~SDHCI_CTRL_8BITBUS;
	453	if (mmc->bus_width == 4)
	454	ctrl \|= SDHCI_CTRL_4BITBUS;
	455	else
	456	ctrl &= ~SDHCI_CTRL_4BITBUS;
	457	}
	458
	459	if (mmc->clock > 26000000)
	460	ctrl \|= SDHCI_CTRL_HISPD;
	461	else
	462	ctrl &= ~SDHCI_CTRL_HISPD;
	463
88a57125 HS	464	if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) \|\|
88a57125 HS	465	(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
236bfecf JC	466	ctrl &= ~SDHCI_CTRL_HISPD;
236bfecf JC	467
af62a557	468	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
07b0b9c0	469
210841c6 SR	470	/* If available, call the driver specific "post" set_ios() function */
	471	if (host->ops && host->ops->set_ios_post)
	472	host->ops->set_ios_post(host);
	473
ef1e4eda	474	return 0;
af62a557 LW	475	}
af62a557 LW	476
6588c78b	477	static int sdhci_init(struct mmc *mmc)
af62a557	478	{
93bfd616	479	struct sdhci_host *host = mmc->priv;
af62a557	480
8d549b61 MY	481	sdhci_reset(host, SDHCI_RESET_ALL);
8d549b61 MY	482
af62a557 LW	483	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
	484	aligned_buffer = memalign(8, 512*1024);
	485	if (!aligned_buffer) {
30e6d979 DR	486	printf("%s: Aligned buffer alloc failed!!!\n",
30e6d979 DR	487	__func__);
2cb5d67c	488	return -ENOMEM;
af62a557 LW	489	}
	490	}
	491
93bfd616	492	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75	493
bf9c4d14	494	if (host->ops && host->ops->get_cd)
6f88a3a5	495	host->ops->get_cd(host);
470dcc75	496
ce0c1bc1	497	/* Enable only interrupts served by the SD controller */
30e6d979 DR	498	sdhci_writel(host, SDHCI_INT_DATA_MASK \| SDHCI_INT_CMD_MASK,
30e6d979 DR	499	SDHCI_INT_ENABLE);
ce0c1bc1 ŁM	500	/* Mask all sdhci interrupt sources */
ce0c1bc1 ŁM	501	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557	502
af62a557 LW	503	return 0;
	504	}
	505
e7881d85	506	#ifdef CONFIG_DM_MMC
ef1e4eda SG	507	int sdhci_probe(struct udevice *dev)
	508	{
	509	struct mmc *mmc = mmc_get_mmc_dev(dev);
	510
	511	return sdhci_init(mmc);
	512	}
ab769f22	513
ef1e4eda SG	514	const struct dm_mmc_ops sdhci_ops = {
	515	.send_cmd = sdhci_send_command,
	516	.set_ios = sdhci_set_ios,
	517	};
	518	#else
ab769f22 PA	519	static const struct mmc_ops sdhci_ops = {
	520	.send_cmd = sdhci_send_command,
	521	.set_ios = sdhci_set_ios,
	522	.init = sdhci_init,
	523	};
ef1e4eda	524	#endif
ab769f22	525
14bed52d	526	int sdhci_setup_cfg(struct mmc_config cfg, struct sdhci_host host,
6d0e34bf	527	u32 f_max, u32 f_min)
af62a557	528	{
6dffdbc3	529	u32 caps, caps_1;
14bed52d JC	530
14bed52d JC	531	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
15bd0995	532
45a68fe2	533	#ifdef CONFIG_MMC_SDHCI_SDMA
15bd0995 MY	534	if (!(caps & SDHCI_CAN_DO_SDMA)) {
	535	printf("%s: Your controller doesn't support SDMA!!\n",
	536	__func__);
	537	return -EINVAL;
	538	}
	539	#endif
895549a2 JC	540	if (host->quirks & SDHCI_QUIRK_REG32_RW)
	541	host->version =
	542	sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
	543	else
	544	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
14bed52d JC	545
14bed52d JC	546	cfg->name = host->name;
e7881d85	547	#ifndef CONFIG_DM_MMC
2a809093	548	cfg->ops = &sdhci_ops;
af62a557	549	#endif
0e0dcc19 WY	550
	551	/* Check whether the clock multiplier is supported or not */
	552	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
	553	caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	554	host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
	555	SDHCI_CLOCK_MUL_SHIFT;
	556	}
	557
6d0e34bf	558	if (host->max_clk == 0) {
14bed52d	559	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
6d0e34bf	560	host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
2a809093	561	SDHCI_CLOCK_BASE_SHIFT;
af62a557	562	else
6d0e34bf	563	host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
2a809093	564	SDHCI_CLOCK_BASE_SHIFT;
6d0e34bf	565	host->max_clk *= 1000000;
0e0dcc19 WY	566	if (host->clk_mul)
0e0dcc19 WY	567	host->max_clk *= host->clk_mul;
af62a557	568	}
6d0e34bf	569	if (host->max_clk == 0) {
6c67954c MY	570	printf("%s: Hardware doesn't specify base clock frequency\n",
6c67954c MY	571	__func__);
2a809093	572	return -EINVAL;
6c67954c	573	}
6d0e34bf SH	574	if (f_max && (f_max < host->max_clk))
	575	cfg->f_max = f_max;
	576	else
	577	cfg->f_max = host->max_clk;
	578	if (f_min)
	579	cfg->f_min = f_min;
af62a557	580	else {
14bed52d	581	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093	582	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
af62a557	583	else
2a809093	584	cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
af62a557	585	}
2a809093	586	cfg->voltages = 0;
af62a557	587	if (caps & SDHCI_CAN_VDD_330)
2a809093	588	cfg->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
af62a557	589	if (caps & SDHCI_CAN_VDD_300)
2a809093	590	cfg->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
af62a557	591	if (caps & SDHCI_CAN_VDD_180)
2a809093	592	cfg->voltages \|= MMC_VDD_165_195;
236bfecf	593
3137e645 MY	594	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
	595	cfg->voltages \|= host->voltages;
	596
be165fbb	597	cfg->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_4BIT;
3fd0a9ba JC	598
3fd0a9ba JC	599	/* Since Host Controller Version3.0 */
14bed52d	600	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
ecd7b246 JC	601	if (!(caps & SDHCI_CAN_DO_8BIT))
ecd7b246 JC	602	cfg->host_caps &= ~MMC_MODE_8BIT;
1695b29a	603	}
42979002	604
88a57125 HS	605	if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
	606	cfg->host_caps &= ~MMC_MODE_HS;
	607	cfg->host_caps &= ~MMC_MODE_HS_52MHz;
	608	}
	609
14bed52d JC	610	if (host->host_caps)
14bed52d JC	611	cfg->host_caps \|= host->host_caps;
42979002	612
2a809093	613	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
93bfd616	614
2a809093 SG	615	return 0;
	616	}
	617
ef1e4eda SG	618	#ifdef CONFIG_BLK
	619	int sdhci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	620	{
	621	return mmc_bind(dev, mmc, cfg);
	622	}
	623	#else
6d0e34bf	624	int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
2a809093	625	{
6c67954c MY	626	int ret;
6c67954c MY	627
6d0e34bf	628	ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
6c67954c MY	629	if (ret)
6c67954c MY	630	return ret;
2a809093	631
93bfd616 PA	632	host->mmc = mmc_create(&host->cfg, host);
	633	if (host->mmc == NULL) {
	634	printf("%s: mmc create fail!\n", __func__);
2cb5d67c	635	return -ENOMEM;
93bfd616	636	}
af62a557 LW	637
	638	return 0;
	639	}
ef1e4eda	640	#endif