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b940ca64 GR |
1 | /* |
2 | * Copyright (C) 2014 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
21c69870 | 6 | #include <common.h> |
b940ca64 | 7 | #include <errno.h> |
84b8bf6d | 8 | #include <linux/bug.h> |
b940ca64 | 9 | #include <asm/io.h> |
21c69870 SY |
10 | #include <libfdt.h> |
11 | #include <fdt_support.h> | |
7b3bd9a7 GR |
12 | #include <fsl-mc/fsl_mc.h> |
13 | #include <fsl-mc/fsl_mc_sys.h> | |
a2a55e51 | 14 | #include <fsl-mc/fsl_mc_private.h> |
7b3bd9a7 | 15 | #include <fsl-mc/fsl_dpmng.h> |
a2a55e51 PK |
16 | #include <fsl-mc/fsl_dprc.h> |
17 | #include <fsl-mc/fsl_dpio.h> | |
fb4a87a7 | 18 | #include <fsl-mc/fsl_dpni.h> |
a2a55e51 | 19 | #include <fsl-mc/fsl_qbman_portal.h> |
fb4a87a7 | 20 | #include <fsl-mc/ldpaa_wriop.h> |
b940ca64 | 21 | |
125e2bc1 GR |
22 | #define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024) |
23 | #define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1)) | |
24 | #define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024) | |
25 | ||
26 | #define MC_MEM_SIZE_ENV_VAR "mcmemsize" | |
27 | #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" | |
28 | ||
b940ca64 | 29 | DECLARE_GLOBAL_DATA_PTR; |
fb4a87a7 PK |
30 | static int mc_boot_status = -1; |
31 | static int mc_dpl_applied = -1; | |
32 | #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET | |
33 | static int mc_aiop_applied = -1; | |
34 | #endif | |
1730a17d PK |
35 | struct fsl_mc_io *root_mc_io = NULL; |
36 | struct fsl_mc_io *dflt_mc_io = NULL; /* child container */ | |
37 | uint16_t root_dprc_handle = 0; | |
a2a55e51 | 38 | uint16_t dflt_dprc_handle = 0; |
1730a17d | 39 | int child_dprc_id; |
a2a55e51 PK |
40 | struct fsl_dpbp_obj *dflt_dpbp = NULL; |
41 | struct fsl_dpio_obj *dflt_dpio = NULL; | |
1730a17d | 42 | struct fsl_dpni_obj *dflt_dpni = NULL; |
125e2bc1 GR |
43 | |
44 | #ifdef DEBUG | |
45 | void dump_ram_words(const char *title, void *addr) | |
46 | { | |
47 | int i; | |
48 | uint32_t *words = addr; | |
49 | ||
50 | printf("Dumping beginning of %s (%p):\n", title, addr); | |
51 | for (i = 0; i < 16; i++) | |
52 | printf("%#x ", words[i]); | |
53 | ||
54 | printf("\n"); | |
55 | } | |
b940ca64 | 56 | |
125e2bc1 GR |
57 | void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs) |
58 | { | |
59 | printf("MC CCSR registers:\n" | |
60 | "reg_gcr1 %#x\n" | |
61 | "reg_gsr %#x\n" | |
62 | "reg_sicbalr %#x\n" | |
63 | "reg_sicbahr %#x\n" | |
64 | "reg_sicapr %#x\n" | |
65 | "reg_mcfbalr %#x\n" | |
66 | "reg_mcfbahr %#x\n" | |
67 | "reg_mcfapr %#x\n" | |
68 | "reg_psr %#x\n", | |
69 | mc_ccsr_regs->reg_gcr1, | |
70 | mc_ccsr_regs->reg_gsr, | |
71 | mc_ccsr_regs->reg_sicbalr, | |
72 | mc_ccsr_regs->reg_sicbahr, | |
73 | mc_ccsr_regs->reg_sicapr, | |
74 | mc_ccsr_regs->reg_mcfbalr, | |
75 | mc_ccsr_regs->reg_mcfbahr, | |
76 | mc_ccsr_regs->reg_mcfapr, | |
77 | mc_ccsr_regs->reg_psr); | |
78 | } | |
79 | #else | |
80 | ||
81 | #define dump_ram_words(title, addr) | |
82 | #define dump_mc_ccsr_regs(mc_ccsr_regs) | |
83 | ||
84 | #endif /* DEBUG */ | |
85 | ||
86 | #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR | |
b940ca64 GR |
87 | /** |
88 | * Copying MC firmware or DPL image to DDR | |
89 | */ | |
90 | static int mc_copy_image(const char *title, | |
7b3bd9a7 | 91 | u64 image_addr, u32 image_size, u64 mc_ram_addr) |
b940ca64 GR |
92 | { |
93 | debug("%s copied to address %p\n", title, (void *)mc_ram_addr); | |
94 | memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); | |
125e2bc1 | 95 | flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size); |
b940ca64 GR |
96 | return 0; |
97 | } | |
98 | ||
99 | /** | |
100 | * MC firmware FIT image parser checks if the image is in FIT | |
101 | * format, verifies integrity of the image and calculates | |
102 | * raw image address and size values. | |
7b3bd9a7 | 103 | * Returns 0 on success and a negative errno on error. |
b940ca64 GR |
104 | * task fail. |
105 | **/ | |
fb4a87a7 PK |
106 | int parse_mc_firmware_fit_image(u64 mc_fw_addr, |
107 | const void **raw_image_addr, | |
b940ca64 GR |
108 | size_t *raw_image_size) |
109 | { | |
110 | int format; | |
111 | void *fit_hdr; | |
112 | int node_offset; | |
113 | const void *data; | |
114 | size_t size; | |
115 | const char *uname = "firmware"; | |
116 | ||
fb4a87a7 | 117 | fit_hdr = (void *)mc_fw_addr; |
b940ca64 GR |
118 | |
119 | /* Check if Image is in FIT format */ | |
120 | format = genimg_get_format(fit_hdr); | |
121 | ||
122 | if (format != IMAGE_FORMAT_FIT) { | |
fb4a87a7 | 123 | printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n"); |
7b3bd9a7 | 124 | return -EINVAL; |
b940ca64 GR |
125 | } |
126 | ||
127 | if (!fit_check_format(fit_hdr)) { | |
fb4a87a7 | 128 | printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n"); |
7b3bd9a7 | 129 | return -EINVAL; |
b940ca64 GR |
130 | } |
131 | ||
132 | node_offset = fit_image_get_node(fit_hdr, uname); | |
133 | ||
134 | if (node_offset < 0) { | |
fb4a87a7 | 135 | printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n"); |
7b3bd9a7 | 136 | return -ENOENT; |
b940ca64 GR |
137 | } |
138 | ||
139 | /* Verify MC firmware image */ | |
140 | if (!(fit_image_verify(fit_hdr, node_offset))) { | |
fb4a87a7 | 141 | printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n"); |
7b3bd9a7 | 142 | return -EINVAL; |
b940ca64 GR |
143 | } |
144 | ||
145 | /* Get address and size of raw image */ | |
146 | fit_image_get_data(fit_hdr, node_offset, &data, &size); | |
147 | ||
148 | *raw_image_addr = data; | |
149 | *raw_image_size = size; | |
150 | ||
151 | return 0; | |
152 | } | |
125e2bc1 GR |
153 | #endif |
154 | ||
155 | /* | |
156 | * Calculates the values to be used to specify the address range | |
157 | * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers. | |
158 | * It returns the highest 512MB-aligned address within the given | |
159 | * address range, in '*aligned_base_addr', and the number of 256 MiB | |
160 | * blocks in it, in 'num_256mb_blocks'. | |
161 | */ | |
162 | static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, | |
163 | size_t mc_ram_size, | |
164 | u64 *aligned_base_addr, | |
165 | u8 *num_256mb_blocks) | |
166 | { | |
167 | u64 addr; | |
168 | u16 num_blocks; | |
169 | ||
170 | if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) { | |
171 | printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", | |
172 | mc_ram_size); | |
173 | return -EINVAL; | |
174 | } | |
175 | ||
176 | num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; | |
177 | if (num_blocks < 1 || num_blocks > 0xff) { | |
178 | printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", | |
179 | mc_ram_size); | |
180 | return -EINVAL; | |
181 | } | |
182 | ||
183 | addr = (mc_private_ram_start_addr + mc_ram_size - 1) & | |
184 | MC_RAM_BASE_ADDR_ALIGNMENT_MASK; | |
185 | ||
186 | if (addr < mc_private_ram_start_addr) { | |
187 | printf("fsl-mc: ERROR: bad start address %#llx\n", | |
188 | mc_private_ram_start_addr); | |
189 | return -EFAULT; | |
190 | } | |
191 | ||
192 | *aligned_base_addr = addr; | |
193 | *num_256mb_blocks = num_blocks; | |
194 | return 0; | |
195 | } | |
196 | ||
21c69870 SY |
197 | static int mc_fixup_dpc(u64 dpc_addr) |
198 | { | |
199 | void *blob = (void *)dpc_addr; | |
200 | int nodeoffset; | |
201 | ||
202 | /* delete any existing ICID pools */ | |
203 | nodeoffset = fdt_path_offset(blob, "/resources/icid_pools"); | |
204 | if (fdt_del_node(blob, nodeoffset) < 0) | |
205 | printf("\nfsl-mc: WARNING: could not delete ICID pool\n"); | |
206 | ||
207 | /* add a new pool */ | |
208 | nodeoffset = fdt_path_offset(blob, "/resources"); | |
209 | if (nodeoffset < 0) { | |
210 | printf("\nfsl-mc: ERROR: DPC is missing /resources\n"); | |
211 | return -EINVAL; | |
212 | } | |
213 | nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools"); | |
214 | nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0"); | |
215 | do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", | |
216 | "base_icid", FSL_DPAA2_STREAM_ID_START, 1); | |
217 | do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0", | |
218 | "num", | |
219 | FSL_DPAA2_STREAM_ID_END - | |
220 | FSL_DPAA2_STREAM_ID_START + 1, 1); | |
221 | ||
222 | flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
fb4a87a7 | 227 | static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) |
125e2bc1 GR |
228 | { |
229 | u64 mc_dpc_offset; | |
230 | #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR | |
231 | int error; | |
232 | void *dpc_fdt_hdr; | |
233 | int dpc_size; | |
234 | #endif | |
235 | ||
236 | #ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET | |
237 | BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || | |
238 | CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); | |
239 | ||
240 | mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; | |
241 | #else | |
242 | #error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" | |
243 | #endif | |
244 | ||
245 | /* | |
246 | * Load the MC DPC blob in the MC private DRAM block: | |
247 | */ | |
248 | #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR | |
249 | printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset); | |
250 | #else | |
251 | /* | |
252 | * Get address and size of the DPC blob stored in flash: | |
253 | */ | |
fb4a87a7 | 254 | dpc_fdt_hdr = (void *)mc_dpc_addr; |
125e2bc1 GR |
255 | |
256 | error = fdt_check_header(dpc_fdt_hdr); | |
257 | if (error != 0) { | |
258 | /* | |
259 | * Don't return with error here, since the MC firmware can | |
260 | * still boot without a DPC | |
261 | */ | |
cc088c3a | 262 | printf("\nfsl-mc: WARNING: No DPC image found"); |
125e2bc1 GR |
263 | return 0; |
264 | } | |
265 | ||
266 | dpc_size = fdt_totalsize(dpc_fdt_hdr); | |
267 | if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { | |
cc088c3a | 268 | printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", |
125e2bc1 GR |
269 | dpc_size); |
270 | return -EINVAL; | |
271 | } | |
272 | ||
273 | mc_copy_image("MC DPC blob", | |
274 | (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset); | |
275 | #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */ | |
276 | ||
21c69870 SY |
277 | if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset)) |
278 | return -EINVAL; | |
279 | ||
125e2bc1 GR |
280 | dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset)); |
281 | return 0; | |
282 | } | |
283 | ||
fb4a87a7 | 284 | static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) |
125e2bc1 GR |
285 | { |
286 | u64 mc_dpl_offset; | |
287 | #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR | |
288 | int error; | |
289 | void *dpl_fdt_hdr; | |
290 | int dpl_size; | |
291 | #endif | |
292 | ||
293 | #ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET | |
294 | BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || | |
295 | CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); | |
296 | ||
297 | mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; | |
298 | #else | |
299 | #error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" | |
300 | #endif | |
301 | ||
302 | /* | |
303 | * Load the MC DPL blob in the MC private DRAM block: | |
304 | */ | |
305 | #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR | |
306 | printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset); | |
307 | #else | |
308 | /* | |
309 | * Get address and size of the DPL blob stored in flash: | |
310 | */ | |
fb4a87a7 | 311 | dpl_fdt_hdr = (void *)mc_dpl_addr; |
125e2bc1 GR |
312 | |
313 | error = fdt_check_header(dpl_fdt_hdr); | |
314 | if (error != 0) { | |
cc088c3a | 315 | printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n"); |
125e2bc1 GR |
316 | return error; |
317 | } | |
318 | ||
319 | dpl_size = fdt_totalsize(dpl_fdt_hdr); | |
320 | if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { | |
cc088c3a | 321 | printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", |
125e2bc1 GR |
322 | dpl_size); |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | mc_copy_image("MC DPL blob", | |
327 | (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); | |
328 | #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */ | |
329 | ||
330 | dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset)); | |
331 | return 0; | |
332 | } | |
333 | ||
334 | /** | |
335 | * Return the MC boot timeout value in milliseconds | |
336 | */ | |
337 | static unsigned long get_mc_boot_timeout_ms(void) | |
338 | { | |
339 | unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; | |
340 | ||
341 | char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR); | |
342 | ||
343 | if (timeout_ms_env_var) { | |
344 | timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10); | |
345 | if (timeout_ms == 0) { | |
346 | printf("fsl-mc: WARNING: Invalid value for \'" | |
347 | MC_BOOT_TIMEOUT_ENV_VAR | |
348 | "\' environment variable: %lu\n", | |
349 | timeout_ms); | |
350 | ||
351 | timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; | |
352 | } | |
353 | } | |
354 | ||
355 | return timeout_ms; | |
356 | } | |
357 | ||
fb4a87a7 PK |
358 | #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET |
359 | static int load_mc_aiop_img(u64 aiop_fw_addr) | |
c1000c12 | 360 | { |
fb4a87a7 PK |
361 | u64 mc_ram_addr = mc_get_dram_addr(); |
362 | #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR | |
c1000c12 | 363 | void *aiop_img; |
fb4a87a7 | 364 | #endif |
c1000c12 GR |
365 | |
366 | /* | |
367 | * Load the MC AIOP image in the MC private DRAM block: | |
368 | */ | |
369 | ||
fb4a87a7 PK |
370 | #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR |
371 | printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + | |
372 | CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); | |
373 | #else | |
374 | aiop_img = (void *)aiop_fw_addr; | |
c1000c12 GR |
375 | mc_copy_image("MC AIOP image", |
376 | (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, | |
377 | mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); | |
fb4a87a7 PK |
378 | #endif |
379 | mc_aiop_applied = 0; | |
c1000c12 GR |
380 | |
381 | return 0; | |
382 | } | |
383 | #endif | |
fb4a87a7 | 384 | |
125e2bc1 GR |
385 | static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) |
386 | { | |
387 | u32 reg_gsr; | |
388 | u32 mc_fw_boot_status; | |
389 | unsigned long timeout_ms = get_mc_boot_timeout_ms(); | |
390 | struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; | |
391 | ||
392 | dmb(); | |
125e2bc1 GR |
393 | assert(timeout_ms > 0); |
394 | for (;;) { | |
395 | udelay(1000); /* throttle polling */ | |
396 | reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); | |
397 | mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); | |
398 | if (mc_fw_boot_status & 0x1) | |
399 | break; | |
400 | ||
401 | timeout_ms--; | |
402 | if (timeout_ms == 0) | |
403 | break; | |
404 | } | |
405 | ||
406 | if (timeout_ms == 0) { | |
cc088c3a | 407 | printf("ERROR: timeout\n"); |
125e2bc1 GR |
408 | |
409 | /* TODO: Get an error status from an MC CCSR register */ | |
410 | return -ETIMEDOUT; | |
411 | } | |
412 | ||
413 | if (mc_fw_boot_status != 0x1) { | |
414 | /* | |
415 | * TODO: Identify critical errors from the GSR register's FS | |
416 | * field and for those errors, set error to -ENODEV or other | |
417 | * appropriate errno, so that the status property is set to | |
418 | * failure in the fsl,dprc device tree node. | |
419 | */ | |
cc088c3a GR |
420 | printf("WARNING: Firmware returned an error (GSR: %#x)\n", |
421 | reg_gsr); | |
422 | } else { | |
423 | printf("SUCCESS\n"); | |
125e2bc1 GR |
424 | } |
425 | ||
cc088c3a | 426 | |
125e2bc1 GR |
427 | *final_reg_gsr = reg_gsr; |
428 | return 0; | |
429 | } | |
b940ca64 | 430 | |
fb4a87a7 | 431 | int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) |
b940ca64 GR |
432 | { |
433 | int error = 0; | |
a2a55e51 | 434 | int portal_id = 0; |
b940ca64 | 435 | struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; |
fb4a87a7 | 436 | u64 mc_ram_addr = mc_get_dram_addr(); |
b940ca64 | 437 | u32 reg_gsr; |
125e2bc1 GR |
438 | u32 reg_mcfbalr; |
439 | #ifndef CONFIG_SYS_LS_MC_FW_IN_DDR | |
b940ca64 GR |
440 | const void *raw_image_addr; |
441 | size_t raw_image_size = 0; | |
125e2bc1 | 442 | #endif |
7b3bd9a7 | 443 | struct mc_version mc_ver_info; |
125e2bc1 GR |
444 | u64 mc_ram_aligned_base_addr; |
445 | u8 mc_ram_num_256mb_blocks; | |
446 | size_t mc_ram_size = mc_get_dram_block_size(); | |
b940ca64 | 447 | |
b940ca64 | 448 | |
125e2bc1 GR |
449 | error = calculate_mc_private_ram_params(mc_ram_addr, |
450 | mc_ram_size, | |
451 | &mc_ram_aligned_base_addr, | |
452 | &mc_ram_num_256mb_blocks); | |
453 | if (error != 0) | |
454 | goto out; | |
455 | ||
b940ca64 GR |
456 | /* |
457 | * Management Complex cores should be held at reset out of POR. | |
458 | * U-boot should be the first software to touch MC. To be safe, | |
459 | * we reset all cores again by setting GCR1 to 0. It doesn't do | |
460 | * anything if they are held at reset. After we setup the firmware | |
461 | * we kick off MC by deasserting the reset bit for core 0, and | |
462 | * deasserting the reset bits for Command Portal Managers. | |
463 | * The stop bits are not touched here. They are used to stop the | |
464 | * cores when they are active. Setting stop bits doesn't stop the | |
465 | * cores from fetching instructions when they are released from | |
466 | * reset. | |
467 | */ | |
468 | out_le32(&mc_ccsr_regs->reg_gcr1, 0); | |
469 | dmb(); | |
470 | ||
125e2bc1 GR |
471 | #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR |
472 | printf("MC firmware is preloaded to %#llx\n", mc_ram_addr); | |
473 | #else | |
fb4a87a7 PK |
474 | error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr, |
475 | &raw_image_size); | |
b940ca64 GR |
476 | if (error != 0) |
477 | goto out; | |
478 | /* | |
479 | * Load the MC FW at the beginning of the MC private DRAM block: | |
480 | */ | |
7b3bd9a7 GR |
481 | mc_copy_image("MC Firmware", |
482 | (u64)raw_image_addr, raw_image_size, mc_ram_addr); | |
7b3bd9a7 | 483 | #endif |
125e2bc1 | 484 | dump_ram_words("firmware", (void *)mc_ram_addr); |
7b3bd9a7 | 485 | |
fb4a87a7 | 486 | error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr); |
125e2bc1 | 487 | if (error != 0) |
b940ca64 | 488 | goto out; |
b940ca64 GR |
489 | |
490 | debug("mc_ccsr_regs %p\n", mc_ccsr_regs); | |
125e2bc1 | 491 | dump_mc_ccsr_regs(mc_ccsr_regs); |
b940ca64 GR |
492 | |
493 | /* | |
125e2bc1 | 494 | * Tell MC what is the address range of the DRAM block assigned to it: |
b940ca64 | 495 | */ |
125e2bc1 GR |
496 | reg_mcfbalr = (u32)mc_ram_aligned_base_addr | |
497 | (mc_ram_num_256mb_blocks - 1); | |
498 | out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); | |
499 | out_le32(&mc_ccsr_regs->reg_mcfbahr, | |
500 | (u32)(mc_ram_aligned_base_addr >> 32)); | |
39da644e | 501 | out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ); |
b940ca64 GR |
502 | |
503 | /* | |
125e2bc1 | 504 | * Tell the MC that we want delayed DPL deployment. |
b940ca64 | 505 | */ |
125e2bc1 | 506 | out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00); |
b940ca64 | 507 | |
cc088c3a | 508 | printf("\nfsl-mc: Booting Management Complex ... "); |
7b3bd9a7 | 509 | |
b940ca64 GR |
510 | /* |
511 | * Deassert reset and release MC core 0 to run | |
512 | */ | |
513 | out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); | |
125e2bc1 GR |
514 | error = wait_for_mc(true, ®_gsr); |
515 | if (error != 0) | |
b940ca64 | 516 | goto out; |
b940ca64 | 517 | |
7b3bd9a7 GR |
518 | /* |
519 | * TODO: need to obtain the portal_id for the root container from the | |
520 | * DPL | |
521 | */ | |
522 | portal_id = 0; | |
523 | ||
524 | /* | |
a2a55e51 PK |
525 | * Initialize the global default MC portal |
526 | * And check that the MC firmware is responding portal commands: | |
7b3bd9a7 | 527 | */ |
1730a17d PK |
528 | root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); |
529 | if (!root_mc_io) { | |
a2a55e51 PK |
530 | printf(" No memory: malloc() failed\n"); |
531 | return -ENOMEM; | |
532 | } | |
533 | ||
1730a17d | 534 | root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); |
7b3bd9a7 | 535 | debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", |
1730a17d | 536 | portal_id, root_mc_io->mmio_regs); |
7b3bd9a7 | 537 | |
1730a17d | 538 | error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info); |
7b3bd9a7 GR |
539 | if (error != 0) { |
540 | printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", | |
541 | error); | |
542 | goto out; | |
543 | } | |
544 | ||
7b3bd9a7 GR |
545 | printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", |
546 | mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, | |
125e2bc1 GR |
547 | reg_gsr & GSR_FS_MASK); |
548 | ||
fb4a87a7 PK |
549 | out: |
550 | if (error != 0) | |
551 | mc_boot_status = error; | |
552 | else | |
553 | mc_boot_status = 0; | |
554 | ||
555 | return error; | |
556 | } | |
557 | ||
558 | int mc_apply_dpl(u64 mc_dpl_addr) | |
559 | { | |
560 | struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; | |
561 | int error = 0; | |
562 | u32 reg_gsr; | |
563 | u64 mc_ram_addr = mc_get_dram_addr(); | |
564 | size_t mc_ram_size = mc_get_dram_block_size(); | |
565 | ||
566 | error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr); | |
567 | if (error != 0) | |
568 | return error; | |
569 | ||
125e2bc1 GR |
570 | /* |
571 | * Tell the MC to deploy the DPL: | |
572 | */ | |
573 | out_le32(&mc_ccsr_regs->reg_gsr, 0x0); | |
cc088c3a | 574 | printf("fsl-mc: Deploying data path layout ... "); |
125e2bc1 | 575 | error = wait_for_mc(false, ®_gsr); |
cc088c3a | 576 | |
fb4a87a7 PK |
577 | if (!error) |
578 | mc_dpl_applied = 0; | |
b940ca64 GR |
579 | |
580 | return error; | |
581 | } | |
582 | ||
583 | int get_mc_boot_status(void) | |
584 | { | |
585 | return mc_boot_status; | |
586 | } | |
587 | ||
fb4a87a7 PK |
588 | #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET |
589 | int get_aiop_apply_status(void) | |
590 | { | |
591 | return mc_aiop_applied; | |
592 | } | |
593 | #endif | |
594 | ||
595 | int get_dpl_apply_status(void) | |
596 | { | |
597 | return mc_dpl_applied; | |
598 | } | |
599 | ||
600 | /** | |
601 | * Return the MC address of private DRAM block. | |
602 | */ | |
603 | u64 mc_get_dram_addr(void) | |
604 | { | |
605 | u64 mc_ram_addr; | |
606 | ||
607 | /* | |
608 | * The MC private DRAM block was already carved at the end of DRAM | |
609 | * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: | |
610 | */ | |
611 | if (gd->bd->bi_dram[1].start) { | |
612 | mc_ram_addr = | |
613 | gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; | |
614 | } else { | |
615 | mc_ram_addr = | |
616 | gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; | |
617 | } | |
618 | ||
619 | return mc_ram_addr; | |
620 | } | |
621 | ||
b940ca64 GR |
622 | /** |
623 | * Return the actual size of the MC private DRAM block. | |
b940ca64 GR |
624 | */ |
625 | unsigned long mc_get_dram_block_size(void) | |
626 | { | |
125e2bc1 GR |
627 | unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; |
628 | ||
629 | char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR); | |
630 | ||
631 | if (dram_block_size_env_var) { | |
632 | dram_block_size = simple_strtoul(dram_block_size_env_var, NULL, | |
633 | 10); | |
634 | ||
635 | if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { | |
636 | printf("fsl-mc: WARNING: Invalid value for \'" | |
637 | MC_MEM_SIZE_ENV_VAR | |
638 | "\' environment variable: %lu\n", | |
639 | dram_block_size); | |
640 | ||
641 | dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; | |
642 | } | |
643 | } | |
644 | ||
645 | return dram_block_size; | |
b940ca64 | 646 | } |
a2a55e51 | 647 | |
1730a17d PK |
648 | int fsl_mc_ldpaa_init(bd_t *bis) |
649 | { | |
c919ab9e PK |
650 | int i; |
651 | ||
652 | for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) | |
653 | if ((wriop_is_enabled_dpmac(i) == 1) && | |
654 | (wriop_get_phy_address(i) != -1)) | |
655 | ldpaa_eth_init(i, wriop_get_enet_if(i)); | |
1730a17d PK |
656 | return 0; |
657 | } | |
658 | ||
9a696f56 PK |
659 | static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle) |
660 | { | |
661 | struct dprc_attributes attr; | |
662 | int error; | |
663 | ||
664 | memset(&attr, 0, sizeof(struct dprc_attributes)); | |
665 | error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr); | |
666 | if (error == 0) { | |
667 | if ((attr.version.major != DPRC_VER_MAJOR) || | |
668 | (attr.version.minor != DPRC_VER_MINOR)) { | |
669 | printf("DPRC version mismatch found %u.%u,", | |
670 | attr.version.major, | |
671 | attr.version.minor); | |
672 | printf("supported version is %u.%u\n", | |
673 | DPRC_VER_MAJOR, DPRC_VER_MINOR); | |
674 | } | |
675 | } | |
676 | return error; | |
677 | } | |
678 | ||
1730a17d | 679 | static int dpio_init(void) |
a2a55e51 PK |
680 | { |
681 | struct qbman_swp_desc p_des; | |
682 | struct dpio_attr attr; | |
1730a17d | 683 | struct dpio_cfg dpio_cfg; |
a2a55e51 PK |
684 | int err = 0; |
685 | ||
686 | dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj)); | |
687 | if (!dflt_dpio) { | |
1730a17d PK |
688 | printf("No memory: malloc() failed\n"); |
689 | err = -ENOMEM; | |
690 | goto err_malloc; | |
a2a55e51 PK |
691 | } |
692 | ||
1730a17d PK |
693 | dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL; |
694 | dpio_cfg.num_priorities = 8; | |
a2a55e51 | 695 | |
1730a17d PK |
696 | err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg, |
697 | &dflt_dpio->dpio_handle); | |
698 | if (err < 0) { | |
699 | printf("dpio_create() failed: %d\n", err); | |
700 | err = -ENODEV; | |
701 | goto err_create; | |
a2a55e51 PK |
702 | } |
703 | ||
1730a17d | 704 | memset(&attr, 0, sizeof(struct dpio_attr)); |
87457d11 | 705 | err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, |
1730a17d PK |
706 | dflt_dpio->dpio_handle, &attr); |
707 | if (err < 0) { | |
708 | printf("dpio_get_attributes() failed: %d\n", err); | |
a2a55e51 PK |
709 | goto err_get_attr; |
710 | } | |
711 | ||
9a696f56 PK |
712 | if ((attr.version.major != DPIO_VER_MAJOR) || |
713 | (attr.version.minor != DPIO_VER_MINOR)) { | |
714 | printf("DPIO version mismatch found %u.%u,", | |
715 | attr.version.major, attr.version.minor); | |
716 | printf("supported version is %u.%u\n", | |
717 | DPIO_VER_MAJOR, DPIO_VER_MINOR); | |
718 | } | |
719 | ||
1730a17d PK |
720 | dflt_dpio->dpio_id = attr.id; |
721 | #ifdef DEBUG | |
722 | printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); | |
723 | #endif | |
1730a17d PK |
724 | err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); |
725 | if (err < 0) { | |
a2a55e51 PK |
726 | printf("dpio_enable() failed %d\n", err); |
727 | goto err_get_enable; | |
728 | } | |
1f1c25c7 PK |
729 | debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n", |
730 | attr.qbman_portal_ce_offset, | |
731 | attr.qbman_portal_ci_offset, | |
a2a55e51 PK |
732 | attr.qbman_portal_id, |
733 | attr.num_priorities); | |
734 | ||
1f1c25c7 PK |
735 | p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR |
736 | + attr.qbman_portal_ce_offset); | |
737 | p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR | |
738 | + attr.qbman_portal_ci_offset); | |
a2a55e51 PK |
739 | |
740 | dflt_dpio->sw_portal = qbman_swp_init(&p_des); | |
741 | if (dflt_dpio->sw_portal == NULL) { | |
742 | printf("qbman_swp_init() failed\n"); | |
743 | goto err_get_swp_init; | |
744 | } | |
745 | return 0; | |
746 | ||
747 | err_get_swp_init: | |
1730a17d | 748 | dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); |
a2a55e51 | 749 | err_get_enable: |
a2a55e51 | 750 | free(dflt_dpio); |
1730a17d PK |
751 | err_get_attr: |
752 | dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); | |
753 | dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); | |
754 | err_create: | |
755 | err_malloc: | |
756 | return err; | |
757 | } | |
758 | ||
759 | static int dpio_exit(void) | |
760 | { | |
761 | int err; | |
762 | ||
763 | err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); | |
764 | if (err < 0) { | |
765 | printf("dpio_disable() failed: %d\n", err); | |
766 | goto err; | |
767 | } | |
768 | ||
769 | err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); | |
770 | if (err < 0) { | |
771 | printf("dpio_destroy() failed: %d\n", err); | |
772 | goto err; | |
773 | } | |
774 | ||
775 | #ifdef DEBUG | |
776 | printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id); | |
777 | #endif | |
778 | ||
779 | if (dflt_dpio) | |
780 | free(dflt_dpio); | |
781 | ||
782 | return 0; | |
783 | err: | |
784 | return err; | |
785 | } | |
786 | ||
787 | static int dprc_init(void) | |
788 | { | |
789 | int err, child_portal_id, container_id; | |
790 | struct dprc_cfg cfg; | |
791 | uint64_t mc_portal_offset; | |
792 | ||
793 | /* Open root container */ | |
794 | err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id); | |
795 | if (err < 0) { | |
796 | printf("dprc_get_container_id(): Root failed: %d\n", err); | |
797 | goto err_root_container_id; | |
798 | } | |
799 | ||
800 | #ifdef DEBUG | |
801 | printf("Root container id = %d\n", container_id); | |
802 | #endif | |
803 | err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id, | |
804 | &root_dprc_handle); | |
805 | if (err < 0) { | |
806 | printf("dprc_open(): Root Container failed: %d\n", err); | |
807 | goto err_root_open; | |
808 | } | |
809 | ||
810 | if (!root_dprc_handle) { | |
811 | printf("dprc_open(): Root Container Handle is not valid\n"); | |
812 | goto err_root_open; | |
813 | } | |
814 | ||
9a696f56 PK |
815 | err = dprc_version_check(root_mc_io, root_dprc_handle); |
816 | if (err < 0) { | |
817 | printf("dprc_version_check() failed: %d\n", err); | |
818 | goto err_root_open; | |
819 | } | |
820 | ||
1730a17d PK |
821 | cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | |
822 | DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | | |
823 | DPRC_CFG_OPT_ALLOC_ALLOWED; | |
824 | cfg.icid = DPRC_GET_ICID_FROM_POOL; | |
335b1936 | 825 | cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL; |
1730a17d PK |
826 | err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, |
827 | root_dprc_handle, | |
828 | &cfg, | |
829 | &child_dprc_id, | |
830 | &mc_portal_offset); | |
831 | if (err < 0) { | |
832 | printf("dprc_create_container() failed: %d\n", err); | |
833 | goto err_create; | |
834 | } | |
835 | ||
836 | dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io)); | |
837 | if (!dflt_mc_io) { | |
838 | err = -ENOMEM; | |
839 | printf(" No memory: malloc() failed\n"); | |
840 | goto err_malloc; | |
841 | } | |
842 | ||
843 | child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset); | |
844 | dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id); | |
845 | #ifdef DEBUG | |
846 | printf("MC portal of child DPRC container: %d, physical addr %p)\n", | |
847 | child_dprc_id, dflt_mc_io->mmio_regs); | |
848 | #endif | |
849 | ||
850 | err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id, | |
851 | &dflt_dprc_handle); | |
852 | if (err < 0) { | |
853 | printf("dprc_open(): Child container failed: %d\n", err); | |
854 | goto err_child_open; | |
855 | } | |
856 | ||
857 | if (!dflt_dprc_handle) { | |
858 | printf("dprc_open(): Child container Handle is not valid\n"); | |
859 | goto err_child_open; | |
860 | } | |
861 | ||
862 | return 0; | |
863 | err_child_open: | |
864 | free(dflt_mc_io); | |
865 | err_malloc: | |
866 | dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, | |
867 | root_dprc_handle, child_dprc_id); | |
868 | err_create: | |
869 | dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); | |
870 | err_root_open: | |
871 | err_root_container_id: | |
872 | return err; | |
873 | } | |
874 | ||
875 | static int dprc_exit(void) | |
876 | { | |
877 | int err; | |
878 | ||
879 | err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle); | |
880 | if (err < 0) { | |
881 | printf("dprc_close(): Child failed: %d\n", err); | |
882 | goto err; | |
883 | } | |
884 | ||
885 | err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS, | |
886 | root_dprc_handle, child_dprc_id); | |
887 | if (err < 0) { | |
888 | printf("dprc_destroy_container() failed: %d\n", err); | |
889 | goto err; | |
890 | } | |
891 | ||
892 | err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle); | |
893 | if (err < 0) { | |
894 | printf("dprc_close(): Root failed: %d\n", err); | |
895 | goto err; | |
896 | } | |
897 | ||
898 | if (dflt_mc_io) | |
899 | free(dflt_mc_io); | |
900 | ||
901 | if (root_mc_io) | |
902 | free(root_mc_io); | |
903 | ||
904 | return 0; | |
905 | ||
906 | err: | |
a2a55e51 PK |
907 | return err; |
908 | } | |
909 | ||
1730a17d | 910 | static int dpbp_init(void) |
a2a55e51 | 911 | { |
1730a17d PK |
912 | int err; |
913 | struct dpbp_attr dpbp_attr; | |
914 | struct dpbp_cfg dpbp_cfg; | |
915 | ||
a2a55e51 PK |
916 | dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj)); |
917 | if (!dflt_dpbp) { | |
1730a17d PK |
918 | printf("No memory: malloc() failed\n"); |
919 | err = -ENOMEM; | |
920 | goto err_malloc; | |
921 | } | |
922 | ||
923 | dpbp_cfg.options = 512; | |
924 | ||
925 | err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg, | |
926 | &dflt_dpbp->dpbp_handle); | |
927 | ||
928 | if (err < 0) { | |
929 | err = -ENODEV; | |
930 | printf("dpbp_create() failed: %d\n", err); | |
931 | goto err_create; | |
932 | } | |
933 | ||
934 | memset(&dpbp_attr, 0, sizeof(struct dpbp_attr)); | |
935 | err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, | |
936 | dflt_dpbp->dpbp_handle, | |
937 | &dpbp_attr); | |
938 | if (err < 0) { | |
939 | printf("dpbp_get_attributes() failed: %d\n", err); | |
940 | goto err_get_attr; | |
941 | } | |
942 | ||
9a696f56 PK |
943 | if ((dpbp_attr.version.major != DPBP_VER_MAJOR) || |
944 | (dpbp_attr.version.minor != DPBP_VER_MINOR)) { | |
945 | printf("DPBP version mismatch found %u.%u,", | |
946 | dpbp_attr.version.major, dpbp_attr.version.minor); | |
947 | printf("supported version is %u.%u\n", | |
948 | DPBP_VER_MAJOR, DPBP_VER_MINOR); | |
949 | } | |
950 | ||
1730a17d PK |
951 | dflt_dpbp->dpbp_attr.id = dpbp_attr.id; |
952 | #ifdef DEBUG | |
953 | printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); | |
954 | #endif | |
955 | ||
956 | err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); | |
957 | if (err < 0) { | |
958 | printf("dpbp_close() failed: %d\n", err); | |
959 | goto err_close; | |
a2a55e51 | 960 | } |
a2a55e51 PK |
961 | |
962 | return 0; | |
1730a17d PK |
963 | |
964 | err_close: | |
965 | free(dflt_dpbp); | |
966 | err_get_attr: | |
967 | dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); | |
968 | dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); | |
969 | err_create: | |
970 | err_malloc: | |
971 | return err; | |
a2a55e51 PK |
972 | } |
973 | ||
1730a17d PK |
974 | static int dpbp_exit(void) |
975 | { | |
976 | int err; | |
977 | ||
978 | err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id, | |
979 | &dflt_dpbp->dpbp_handle); | |
980 | if (err < 0) { | |
981 | printf("dpbp_open() failed: %d\n", err); | |
982 | goto err; | |
983 | } | |
984 | ||
985 | err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, | |
986 | dflt_dpbp->dpbp_handle); | |
987 | if (err < 0) { | |
988 | printf("dpbp_destroy() failed: %d\n", err); | |
989 | goto err; | |
990 | } | |
991 | ||
992 | #ifdef DEBUG | |
993 | printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); | |
994 | #endif | |
995 | ||
996 | if (dflt_dpbp) | |
997 | free(dflt_dpbp); | |
998 | return 0; | |
999 | ||
1000 | err: | |
1001 | return err; | |
1002 | } | |
1003 | ||
1004 | static int dpni_init(void) | |
1005 | { | |
1006 | int err; | |
1007 | struct dpni_attr dpni_attr; | |
879a59ac PK |
1008 | uint8_t ext_cfg_buf[256] = {0}; |
1009 | struct dpni_extended_cfg dpni_extended_cfg; | |
1730a17d PK |
1010 | struct dpni_cfg dpni_cfg; |
1011 | ||
1012 | dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj)); | |
1013 | if (!dflt_dpni) { | |
1014 | printf("No memory: malloc() failed\n"); | |
1015 | err = -ENOMEM; | |
1016 | goto err_malloc; | |
1017 | } | |
1018 | ||
879a59ac PK |
1019 | memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg)); |
1020 | err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]); | |
1021 | if (err < 0) { | |
1022 | err = -ENODEV; | |
1023 | printf("dpni_prepare_extended_cfg() failed: %d\n", err); | |
1024 | goto err_prepare_extended_cfg; | |
1025 | } | |
1026 | ||
1730a17d PK |
1027 | memset(&dpni_cfg, 0, sizeof(dpni_cfg)); |
1028 | dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER | | |
1029 | DPNI_OPT_MULTICAST_FILTER; | |
1030 | ||
879a59ac | 1031 | dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0]; |
1730a17d PK |
1032 | err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg, |
1033 | &dflt_dpni->dpni_handle); | |
1034 | ||
1035 | if (err < 0) { | |
1036 | err = -ENODEV; | |
1037 | printf("dpni_create() failed: %d\n", err); | |
1038 | goto err_create; | |
1039 | } | |
1040 | ||
1041 | memset(&dpni_attr, 0, sizeof(struct dpni_attr)); | |
1042 | err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS, | |
1043 | dflt_dpni->dpni_handle, | |
1044 | &dpni_attr); | |
1045 | if (err < 0) { | |
1046 | printf("dpni_get_attributes() failed: %d\n", err); | |
1047 | goto err_get_attr; | |
1048 | } | |
1049 | ||
9a696f56 PK |
1050 | if ((dpni_attr.version.major != DPNI_VER_MAJOR) || |
1051 | (dpni_attr.version.minor != DPNI_VER_MINOR)) { | |
1052 | printf("DPNI version mismatch found %u.%u,", | |
1053 | dpni_attr.version.major, dpni_attr.version.minor); | |
1054 | printf("supported version is %u.%u\n", | |
1055 | DPNI_VER_MAJOR, DPNI_VER_MINOR); | |
1056 | } | |
1057 | ||
1730a17d PK |
1058 | dflt_dpni->dpni_id = dpni_attr.id; |
1059 | #ifdef DEBUG | |
1060 | printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); | |
1061 | #endif | |
1062 | ||
1063 | err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); | |
1064 | if (err < 0) { | |
1065 | printf("dpni_close() failed: %d\n", err); | |
1066 | goto err_close; | |
1067 | } | |
1068 | ||
1069 | return 0; | |
1070 | ||
1071 | err_close: | |
1730a17d PK |
1072 | err_get_attr: |
1073 | dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); | |
1074 | dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); | |
1075 | err_create: | |
879a59ac PK |
1076 | err_prepare_extended_cfg: |
1077 | free(dflt_dpni); | |
1730a17d PK |
1078 | err_malloc: |
1079 | return err; | |
1080 | } | |
1081 | ||
1082 | static int dpni_exit(void) | |
1083 | { | |
1084 | int err; | |
1085 | ||
1086 | err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id, | |
1087 | &dflt_dpni->dpni_handle); | |
1088 | if (err < 0) { | |
1089 | printf("dpni_open() failed: %d\n", err); | |
1090 | goto err; | |
1091 | } | |
1092 | ||
1093 | err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, | |
1094 | dflt_dpni->dpni_handle); | |
1095 | if (err < 0) { | |
1096 | printf("dpni_destroy() failed: %d\n", err); | |
1097 | goto err; | |
1098 | } | |
1099 | ||
1100 | #ifdef DEBUG | |
1101 | printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id); | |
1102 | #endif | |
1103 | ||
1104 | if (dflt_dpni) | |
1105 | free(dflt_dpni); | |
1106 | return 0; | |
1107 | ||
1108 | err: | |
1109 | return err; | |
1110 | } | |
1111 | ||
1112 | static int mc_init_object(void) | |
a2a55e51 | 1113 | { |
1730a17d PK |
1114 | int err = 0; |
1115 | ||
1116 | err = dprc_init(); | |
1117 | if (err < 0) { | |
1118 | printf("dprc_init() failed: %d\n", err); | |
1119 | goto err; | |
1120 | } | |
1121 | ||
1122 | err = dpbp_init(); | |
1123 | if (err < 0) { | |
1124 | printf("dpbp_init() failed: %d\n", err); | |
1125 | goto err; | |
1126 | } | |
1127 | ||
1128 | err = dpio_init(); | |
1129 | if (err < 0) { | |
1130 | printf("dpio_init() failed: %d\n", err); | |
1131 | goto err; | |
1132 | } | |
1133 | ||
1134 | err = dpni_init(); | |
1135 | if (err < 0) { | |
1136 | printf("dpni_init() failed: %d\n", err); | |
1137 | goto err; | |
1138 | } | |
a2a55e51 | 1139 | |
fb4a87a7 | 1140 | return 0; |
1730a17d PK |
1141 | err: |
1142 | return err; | |
a2a55e51 PK |
1143 | } |
1144 | ||
1730a17d | 1145 | int fsl_mc_ldpaa_exit(bd_t *bd) |
a2a55e51 | 1146 | { |
1730a17d PK |
1147 | int err = 0; |
1148 | ||
1149 | if (bd && get_mc_boot_status() == -1) | |
1150 | return 0; | |
1151 | ||
1152 | if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) { | |
1153 | printf("ERROR: fsl-mc: DPL is not applied\n"); | |
1154 | err = -ENODEV; | |
1155 | return err; | |
1156 | } | |
1157 | ||
1158 | if (bd && !get_mc_boot_status() && !get_dpl_apply_status()) | |
1159 | return err; | |
1160 | ||
1161 | err = dpbp_exit(); | |
1162 | if (err < 0) { | |
1163 | printf("dpni_exit() failed: %d\n", err); | |
1164 | goto err; | |
1165 | } | |
1166 | ||
1167 | err = dpio_exit(); | |
1168 | if (err < 0) { | |
1169 | printf("dpio_exit() failed: %d\n", err); | |
1170 | goto err; | |
1171 | } | |
1172 | ||
1173 | err = dpni_exit(); | |
1174 | if (err < 0) { | |
1175 | printf("dpni_exit() failed: %d\n", err); | |
1176 | goto err; | |
1177 | } | |
1178 | ||
1179 | err = dprc_exit(); | |
1180 | if (err < 0) { | |
1181 | printf("dprc_exit() failed: %d\n", err); | |
1182 | goto err; | |
1183 | } | |
1184 | ||
1185 | return 0; | |
1186 | err: | |
1187 | return err; | |
a2a55e51 PK |
1188 | } |
1189 | ||
fb4a87a7 | 1190 | static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
a2a55e51 | 1191 | { |
fb4a87a7 PK |
1192 | int err = 0; |
1193 | if (argc < 3) | |
1194 | goto usage; | |
1195 | ||
1196 | switch (argv[1][0]) { | |
1197 | case 's': { | |
1198 | char sub_cmd; | |
44937214 PK |
1199 | u64 mc_fw_addr, mc_dpc_addr; |
1200 | #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET | |
1201 | u64 aiop_fw_addr; | |
1202 | #endif | |
fb4a87a7 PK |
1203 | |
1204 | sub_cmd = argv[2][0]; | |
1205 | switch (sub_cmd) { | |
1206 | case 'm': | |
1207 | if (argc < 5) | |
1208 | goto usage; | |
1209 | ||
1210 | if (get_mc_boot_status() == 0) { | |
1211 | printf("fsl-mc: MC is already booted"); | |
1212 | printf("\n"); | |
1213 | return err; | |
1214 | } | |
1215 | mc_fw_addr = simple_strtoull(argv[3], NULL, 16); | |
1216 | mc_dpc_addr = simple_strtoull(argv[4], NULL, | |
1217 | 16); | |
1730a17d PK |
1218 | |
1219 | if (!mc_init(mc_fw_addr, mc_dpc_addr)) | |
1220 | err = mc_init_object(); | |
fb4a87a7 PK |
1221 | break; |
1222 | ||
1223 | #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET | |
1224 | case 'a': | |
1225 | if (argc < 4) | |
1226 | goto usage; | |
1227 | if (get_aiop_apply_status() == 0) { | |
1228 | printf("fsl-mc: AIOP FW is already"); | |
1229 | printf(" applied\n"); | |
1230 | return err; | |
1231 | } | |
1232 | ||
1233 | aiop_fw_addr = simple_strtoull(argv[3], NULL, | |
1234 | 16); | |
1235 | ||
1236 | err = load_mc_aiop_img(aiop_fw_addr); | |
1237 | if (!err) | |
1238 | printf("fsl-mc: AIOP FW applied\n"); | |
1239 | break; | |
1240 | #endif | |
1241 | default: | |
1242 | printf("Invalid option: %s\n", argv[2]); | |
1243 | goto usage; | |
a2a55e51 | 1244 | |
fb4a87a7 PK |
1245 | break; |
1246 | } | |
125e2bc1 | 1247 | } |
fb4a87a7 PK |
1248 | break; |
1249 | ||
1250 | case 'a': { | |
1251 | u64 mc_dpl_addr; | |
1252 | ||
1253 | if (argc < 4) | |
1254 | goto usage; | |
1255 | ||
1256 | if (get_dpl_apply_status() == 0) { | |
1257 | printf("fsl-mc: DPL already applied\n"); | |
1258 | return err; | |
1259 | } | |
1260 | ||
1261 | mc_dpl_addr = simple_strtoull(argv[3], NULL, | |
1262 | 16); | |
1730a17d | 1263 | |
fb4a87a7 PK |
1264 | if (get_mc_boot_status() != 0) { |
1265 | printf("fsl-mc: Deploying data path layout .."); | |
1266 | printf("ERROR (MC is not booted)\n"); | |
1267 | return -ENODEV; | |
1268 | } | |
1730a17d PK |
1269 | |
1270 | if (!fsl_mc_ldpaa_exit(NULL)) | |
1271 | err = mc_apply_dpl(mc_dpl_addr); | |
fb4a87a7 | 1272 | break; |
125e2bc1 | 1273 | } |
fb4a87a7 PK |
1274 | default: |
1275 | printf("Invalid option: %s\n", argv[1]); | |
1276 | goto usage; | |
1277 | break; | |
a2a55e51 | 1278 | } |
fb4a87a7 PK |
1279 | return err; |
1280 | usage: | |
1281 | return CMD_RET_USAGE; | |
a2a55e51 | 1282 | } |
fb4a87a7 PK |
1283 | |
1284 | U_BOOT_CMD( | |
1285 | fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc, | |
1286 | "DPAA2 command to manage Management Complex (MC)", | |
1287 | "start mc [FW_addr] [DPC_addr] - Start Management Complex\n" | |
1288 | "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n" | |
1289 | "fsl_mc start aiop [FW_addr] - Start AIOP\n" | |
1290 | ); |