[thirdparty/u-boot.git] / drivers / pwm / pwm-cadence-ttc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2021 Xilinx, Inc. Michal Simek
 */

#define LOG_CATEGORY UCLASS_PWM

#include <clk.h>
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <log.h>
#include <pwm.h>
#include <asm/io.h>
#include <log.h>
#include <div64.h>
#include <linux/bitfield.h>
#include <linux/math64.h>
#include <linux/log2.h>
#include <linux/time.h>
#include <dm/device_compat.h>

#define CLOCK_CONTROL		0
#define COUNTER_CONTROL		0xc
#define INTERVAL_COUNTER	0x24
#define MATCH_1_COUNTER		0x30

#define CLK_FALLING_EDGE	BIT(6)
#define CLK_SRC_EXTERNAL	BIT(5)
#define CLK_PRESCALE_MASK	GENMASK(4, 1)
#define CLK_PRESCALE_ENABLE	BIT(0)

#define COUNTER_WAVE_POL		BIT(6)
#define COUNTER_WAVE_DISABLE		BIT(5)
#define COUNTER_RESET			BIT(4)
#define COUNTER_MATCH_ENABLE		BIT(3)
#define COUNTER_DECREMENT_ENABLE	BIT(2)
#define COUNTER_INTERVAL_ENABLE		BIT(1)
#define COUNTER_COUNTING_DISABLE	BIT(0)

#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
#define TTC_CLOCK_CONTROL(reg, channel) \
	TTC_REG((reg) + CLOCK_CONTROL, (channel))
#define TTC_COUNTER_CONTROL(reg, channel) \
	TTC_REG((reg) + COUNTER_CONTROL, (channel))
#define TTC_INTERVAL_COUNTER(reg, channel) \
	TTC_REG((reg) + INTERVAL_COUNTER, (channel))
#define TTC_MATCH_1_COUNTER(reg, channel) \
	TTC_REG((reg) + MATCH_1_COUNTER, (channel))

struct cadence_ttc_pwm_plat {
	u8 *regs;
	u32 timer_width;
};

struct cadence_ttc_pwm_priv {
	u8 *regs;
	u32 timer_width;
	u32 timer_mask;
	unsigned long frequency;
	bool invert[2];
};

static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
				      bool polarity)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	priv->invert[channel] = polarity;

	dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);

	return 0;
}

static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
				      uint period_ns, uint duty_ns)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	u32 counter_ctrl, clock_ctrl;
	int period_clocks, duty_clocks, prescaler;

	dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
		duty_ns, period_ns);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	/* Make sure counter is stopped */
	counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
		     COUNTER_COUNTING_DISABLE | COUNTER_WAVE_DISABLE);

	/* Calculate period, prescaler and set clock control register */
	period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
				  NSEC_PER_SEC);

	prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
	if (prescaler < 0)
		prescaler = 0;

	clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));

	if (!prescaler) {
		clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK);
	} else {
		clock_ctrl &= ~CLK_PRESCALE_MASK;
		clock_ctrl |= CLK_PRESCALE_ENABLE;
		clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
	};

	/* External source is not handled by this driver now */
	clock_ctrl &= ~CLK_SRC_EXTERNAL;

	writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));

	/* Calculate interval and set counter control value */
	duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
				NSEC_PER_SEC);

	writel((period_clocks >> prescaler) & priv->timer_mask,
	       TTC_INTERVAL_COUNTER(priv->regs, channel));
	writel((duty_clocks >> prescaler) & priv->timer_mask,
	       TTC_MATCH_1_COUNTER(priv->regs, channel));

	/* Restore/reset counter */
	counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
	counter_ctrl |= COUNTER_INTERVAL_ENABLE |
			COUNTER_RESET |
			COUNTER_MATCH_ENABLE;

	if (priv->invert[channel])
		counter_ctrl |= COUNTER_WAVE_POL;
	else
		counter_ctrl &= ~COUNTER_WAVE_POL;

	writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));

	dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
		period_clocks, prescaler);

	return 0;
};

static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
				      bool enable)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);

	if (enable) {
		clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_COUNTING_DISABLE |
			     COUNTER_WAVE_DISABLE);
		setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_RESET);
	} else {
		setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_COUNTING_DISABLE |
			     COUNTER_WAVE_DISABLE);
	}

	return 0;
};

static int cadence_ttc_pwm_probe(struct udevice *dev)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
	struct clk clk;
	int ret;

	priv->regs = plat->regs;
	priv->timer_width = plat->timer_width;
	priv->timer_mask = GENMASK(priv->timer_width - 1, 0);

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	priv->frequency = clk_get_rate(&clk);
	if (IS_ERR_VALUE(priv->frequency)) {
		dev_err(dev, "failed to get rate\n");
		return priv->frequency;
	}
	dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);

	ret = clk_enable(&clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	return 0;
}

static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
{
	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
	const char *cells;

	cells = dev_read_prop(dev, "#pwm-cells", NULL);
	if (!cells)
		return -EINVAL;

	plat->regs = dev_read_addr_ptr(dev);

	plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);

	return 0;
}

static int cadence_ttc_pwm_bind(struct udevice *dev)
{
	const char *cells;

	cells = dev_read_prop(dev, "#pwm-cells", NULL);
	if (!cells)
		return -ENODEV;

	return 0;
}

static const struct pwm_ops cadence_ttc_pwm_ops = {
	.set_invert = cadence_ttc_pwm_set_invert,
	.set_config = cadence_ttc_pwm_set_config,
	.set_enable = cadence_ttc_pwm_set_enable,
};

static const struct udevice_id cadence_ttc_pwm_ids[] = {
	{ .compatible = "cdns,ttc" },
	{ }
};

U_BOOT_DRIVER(cadence_ttc_pwm) = {
	.name = "cadence_ttc_pwm",
	.id = UCLASS_PWM,
	.of_match = cadence_ttc_pwm_ids,
	.ops = &cadence_ttc_pwm_ops,
	.bind = cadence_ttc_pwm_bind,
	.of_to_plat = cadence_ttc_pwm_of_to_plat,
	.probe = cadence_ttc_pwm_probe,
	.priv_auto = sizeof(struct cadence_ttc_pwm_priv),
	.plat_auto = sizeof(struct cadence_ttc_pwm_plat),
};
Commit	Line	Data
fb92cc2c MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* (C) Copyright 2021 Xilinx, Inc. Michal Simek
	4	*/
	5
	6	#define LOG_CATEGORY UCLASS_PWM
	7
	8	#include <clk.h>
	9	#include <common.h>
	10	#include <div64.h>
	11	#include <dm.h>
	12	#include <log.h>
	13	#include <pwm.h>
	14	#include <asm/io.h>
	15	#include <log.h>
	16	#include <div64.h>
	17	#include <linux/bitfield.h>
	18	#include <linux/math64.h>
	19	#include <linux/log2.h>
13248d66	20	#include <linux/time.h>
fb92cc2c MS	21	#include <dm/device_compat.h>
	22
	23	#define CLOCK_CONTROL 0
	24	#define COUNTER_CONTROL 0xc
	25	#define INTERVAL_COUNTER 0x24
	26	#define MATCH_1_COUNTER 0x30
	27
	28	#define CLK_FALLING_EDGE BIT(6)
	29	#define CLK_SRC_EXTERNAL BIT(5)
	30	#define CLK_PRESCALE_MASK GENMASK(4, 1)
	31	#define CLK_PRESCALE_ENABLE BIT(0)
	32
	33	#define COUNTER_WAVE_POL BIT(6)
	34	#define COUNTER_WAVE_DISABLE BIT(5)
	35	#define COUNTER_RESET BIT(4)
	36	#define COUNTER_MATCH_ENABLE BIT(3)
	37	#define COUNTER_DECREMENT_ENABLE BIT(2)
	38	#define COUNTER_INTERVAL_ENABLE BIT(1)
	39	#define COUNTER_COUNTING_DISABLE BIT(0)
	40
fb92cc2c MS	41	#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
	42	#define TTC_CLOCK_CONTROL(reg, channel) \
	43	TTC_REG((reg) + CLOCK_CONTROL, (channel))
	44	#define TTC_COUNTER_CONTROL(reg, channel) \
	45	TTC_REG((reg) + COUNTER_CONTROL, (channel))
	46	#define TTC_INTERVAL_COUNTER(reg, channel) \
	47	TTC_REG((reg) + INTERVAL_COUNTER, (channel))
	48	#define TTC_MATCH_1_COUNTER(reg, channel) \
	49	TTC_REG((reg) + MATCH_1_COUNTER, (channel))
	50
	51	struct cadence_ttc_pwm_plat {
	52	u8 *regs;
	53	u32 timer_width;
	54	};
	55
	56	struct cadence_ttc_pwm_priv {
	57	u8 *regs;
	58	u32 timer_width;
	59	u32 timer_mask;
	60	unsigned long frequency;
	61	bool invert[2];
	62	};
	63
	64	static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
	65	bool polarity)
	66	{
	67	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	68
	69	if (channel > 2) {
	70	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
	71	return -EINVAL;
	72	}
	73
	74	priv->invert[channel] = polarity;
	75
	76	dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
	77
	78	return 0;
	79	}
	80
	81	static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
	82	uint period_ns, uint duty_ns)
	83	{
	84	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	85	u32 counter_ctrl, clock_ctrl;
	86	int period_clocks, duty_clocks, prescaler;
	87
	88	dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
	89	duty_ns, period_ns);
	90
	91	if (channel > 2) {
	92	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
	93	return -EINVAL;
	94	}
	95
	96	/* Make sure counter is stopped */
	97	counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
	98	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
	99	COUNTER_COUNTING_DISABLE \| COUNTER_WAVE_DISABLE);
	100
	101	/* Calculate period, prescaler and set clock control register */
	102	period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
	103	NSEC_PER_SEC);
	104
105	prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
106	if (prescaler < 0)
107	prescaler = 0;
108
109	clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));
110
111	if (!prescaler) {
112	clock_ctrl &= ~(CLK_PRESCALE_ENABLE \| CLK_PRESCALE_MASK);
113	} else {
114	clock_ctrl &= ~CLK_PRESCALE_MASK;
115	clock_ctrl \|= CLK_PRESCALE_ENABLE;
116	clock_ctrl \|= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
117	};
118
119	/* External source is not handled by this driver now */
120	clock_ctrl &= ~CLK_SRC_EXTERNAL;
121
122	writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));
123
124	/* Calculate interval and set counter control value */
125	duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
126	NSEC_PER_SEC);
127
128	writel((period_clocks >> prescaler) & priv->timer_mask,
129	TTC_INTERVAL_COUNTER(priv->regs, channel));
130	writel((duty_clocks >> prescaler) & priv->timer_mask,
131	TTC_MATCH_1_COUNTER(priv->regs, channel));
132
133	/* Restore/reset counter */
134	counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
135	counter_ctrl \|= COUNTER_INTERVAL_ENABLE \|
136	COUNTER_RESET \|
137	COUNTER_MATCH_ENABLE;
138
139	if (priv->invert[channel])
140	counter_ctrl \|= COUNTER_WAVE_POL;
141	else
142	counter_ctrl &= ~COUNTER_WAVE_POL;
143
144	writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));
145
146	dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
147	period_clocks, prescaler);
148
149	return 0;
150	};
151
152	static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
153	bool enable)
154	{
155	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
156
157	if (channel > 2) {
158	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
159	return -EINVAL;
160	}
161
162	dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
163
164	if (enable) {
165	clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
166	COUNTER_COUNTING_DISABLE \|
167	COUNTER_WAVE_DISABLE);
168	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
169	COUNTER_RESET);
170	} else {
171	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
172	COUNTER_COUNTING_DISABLE \|
173	COUNTER_WAVE_DISABLE);
174	}
175
176	return 0;
177	};
178
179	static int cadence_ttc_pwm_probe(struct udevice *dev)
180	{
181	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
182	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
183	struct clk clk;
184	int ret;
185
186	priv->regs = plat->regs;
187	priv->timer_width = plat->timer_width;
188	priv->timer_mask = GENMASK(priv->timer_width - 1, 0);
189
190	ret = clk_get_by_index(dev, 0, &clk);
191	if (ret < 0) {
192	dev_err(dev, "failed to get clock\n");
193	return ret;
194	}
195
196	priv->frequency = clk_get_rate(&clk);
197	if (IS_ERR_VALUE(priv->frequency)) {
198	dev_err(dev, "failed to get rate\n");
199	return priv->frequency;
200	}
201	dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
202
203	ret = clk_enable(&clk);
204	if (ret) {
205	dev_err(dev, "failed to enable clock\n");
206	return ret;
207	}
208
209	return 0;
210	}
211
212	static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
213	{
214	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
215	const char *cells;
216
217	cells = dev_read_prop(dev, "#pwm-cells", NULL);
218	if (!cells)
219	return -EINVAL;
220
221	plat->regs = dev_read_addr_ptr(dev);
222
223	plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);
224
225	return 0;
226	}
227
228	static int cadence_ttc_pwm_bind(struct udevice *dev)
229	{
230	const char *cells;
231
232	cells = dev_read_prop(dev, "#pwm-cells", NULL);
233	if (!cells)
234	return -ENODEV;
235
236	return 0;
237	}
238
239	static const struct pwm_ops cadence_ttc_pwm_ops = {
240	.set_invert = cadence_ttc_pwm_set_invert,
241	.set_config = cadence_ttc_pwm_set_config,
242	.set_enable = cadence_ttc_pwm_set_enable,
243	};
244
245	static const struct udevice_id cadence_ttc_pwm_ids[] = {
246	{ .compatible = "cdns,ttc" },
247	{ }
248	};
249
250	U_BOOT_DRIVER(cadence_ttc_pwm) = {
251	.name = "cadence_ttc_pwm",
252	.id = UCLASS_PWM,
253	.of_match = cadence_ttc_pwm_ids,
254	.ops = &cadence_ttc_pwm_ops,
255	.bind = cadence_ttc_pwm_bind,
256	.of_to_plat = cadence_ttc_pwm_of_to_plat,
257	.probe = cadence_ttc_pwm_probe,
258	.priv_auto = sizeof(struct cadence_ttc_pwm_priv),
259	.plat_auto = sizeof(struct cadence_ttc_pwm_plat),
260	};