[thirdparty/u-boot.git] / drivers / usb / host / xhci-rockchip.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2016 Rockchip, Inc.
 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
 */
#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <usb.h>
#include <watchdog.h>
#include <linux/errno.h>
#include <linux/compat.h>
#include <linux/usb/dwc3.h>
#include <power/regulator.h>

#include <usb/xhci.h>

struct rockchip_xhci_platdata {
	fdt_addr_t hcd_base;
	struct udevice *vbus_supply;
};

/*
 * Contains pointers to register base addresses
 * for the usb controller.
 */
struct rockchip_xhci {
	struct usb_platdata usb_plat;
	struct xhci_ctrl ctrl;
	struct xhci_hccr *hcd;
	struct dwc3 *dwc3_reg;
};

static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	int ret = 0;

	/*
	 * Get the base address for XHCI controller from the device node
	 */
	plat->hcd_base = dev_read_addr(dev);
	if (plat->hcd_base == FDT_ADDR_T_NONE) {
		pr_err("Can't get the XHCI register base address\n");
		return -ENXIO;
	}

	/* Vbus regulator */
	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &plat->vbus_supply);
	if (ret)
		debug("Can't get VBus regulator!\n");

	return 0;
}

/*
 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
 * @dwc: Pointer to our controller context structure
 * @dev: Pointer to ulcass device
 */
static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
				    struct udevice *dev)
{
	u32 reg;
	u32 utmi_bits;

	/* Set dwc3 usb2 phy config */
	reg = readl(&dwc3_reg->g_usb2phycfg[0]);

	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
	if (utmi_bits == 16) {
		reg |= DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	} else if (utmi_bits == 8) {
		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
	}

	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;

	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
}

static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
				   struct udevice *dev)
{
	int ret;

	ret = dwc3_core_init(rkxhci->dwc3_reg);
	if (ret) {
		pr_err("failed to initialize core\n");
		return ret;
	}

	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);

	/* We are hard-coding DWC3 core to Host Mode */
	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);

	return 0;
}

static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
{
	return 0;
}

static int xhci_usb_probe(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	struct rockchip_xhci *ctx = dev_get_priv(dev);
	struct xhci_hcor *hcor;
	int ret;

	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));

	if (plat->vbus_supply) {
		ret = regulator_set_enable(plat->vbus_supply, true);
		if (ret) {
			pr_err("XHCI: failed to set VBus supply\n");
			return ret;
		}
	}

	ret = rockchip_xhci_core_init(ctx, dev);
	if (ret) {
		pr_err("XHCI: failed to initialize controller\n");
		return ret;
	}

	return xhci_register(dev, ctx->hcd, hcor);
}

static int xhci_usb_remove(struct udevice *dev)
{
	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	struct rockchip_xhci *ctx = dev_get_priv(dev);
	int ret;

	ret = xhci_deregister(dev);
	if (ret)
		return ret;
	ret = rockchip_xhci_core_exit(ctx);
	if (ret)
		return ret;

	if (plat->vbus_supply) {
		ret = regulator_set_enable(plat->vbus_supply, false);
		if (ret)
			pr_err("XHCI: failed to set VBus supply\n");
	}

	return ret;
}

static const struct udevice_id xhci_usb_ids[] = {
	{ .compatible = "rockchip,rk3328-xhci" },
	{ }
};

U_BOOT_DRIVER(usb_xhci) = {
	.name	= "xhci_rockchip",
	.id	= UCLASS_USB,
	.of_match = xhci_usb_ids,
	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
	.probe = xhci_usb_probe,
	.remove = xhci_usb_remove,
	.ops	= &xhci_usb_ops,
	.bind	= dm_scan_fdt_dev,
	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};

static const struct udevice_id usb_phy_ids[] = {
	{ .compatible = "rockchip,rk3328-usb3-phy" },
	{ }
};

U_BOOT_DRIVER(usb_phy) = {
	.name = "usb_phy_rockchip",
	.of_match = usb_phy_ids,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b44566c4 M	2	/*
	3	* Copyright (c) 2016 Rockchip, Inc.
	4	* Authors: Daniel Meng <daniel.meng@rock-chips.com>
b44566c4 M	5	*/
	6	#include <common.h>
	7	#include <dm.h>
f7ae49fc	8	#include <log.h>
b44566c4 M	9	#include <malloc.h>
	10	#include <usb.h>
	11	#include <watchdog.h>
5d97dff0	12	#include <linux/errno.h>
b44566c4 M	13	#include <linux/compat.h>
b44566c4 M	14	#include <linux/usb/dwc3.h>
d3cb14b9	15	#include <power/regulator.h>
b44566c4	16
1708a123	17	#include <usb/xhci.h>
b44566c4	18
b44566c4 M	19	struct rockchip_xhci_platdata {
b44566c4 M	20	fdt_addr_t hcd_base;
d3cb14b9	21	struct udevice *vbus_supply;
b44566c4 M	22	};
	23
	24	/*
	25	* Contains pointers to register base addresses
	26	* for the usb controller.
	27	*/
	28	struct rockchip_xhci {
	29	struct usb_platdata usb_plat;
	30	struct xhci_ctrl ctrl;
	31	struct xhci_hccr *hcd;
	32	struct dwc3 *dwc3_reg;
	33	};
	34
	35	static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
	36	{
	37	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
b44566c4 M	38	int ret = 0;
	39
	40	/*
	41	* Get the base address for XHCI controller from the device node
	42	*/
32c8eee3	43	plat->hcd_base = dev_read_addr(dev);
b44566c4	44	if (plat->hcd_base == FDT_ADDR_T_NONE) {
9b643e31	45	pr_err("Can't get the XHCI register base address\n");
b44566c4 M	46	return -ENXIO;
	47	}
	48
d3cb14b9 MD	49	/* Vbus regulator */
	50	ret = device_get_supply_regulator(dev, "vbus-supply",
	51	&plat->vbus_supply);
b44566c4	52	if (ret)
26a8b80f	53	debug("Can't get VBus regulator!\n");
b44566c4 M	54
	55	return 0;
	56	}
	57
	58	/*
	59	* rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
	60	* @dwc: Pointer to our controller context structure
	61	* @dev: Pointer to ulcass device
	62	*/
	63	static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
	64	struct udevice *dev)
	65	{
	66	u32 reg;
b44566c4 M	67	u32 utmi_bits;
	68
	69	/* Set dwc3 usb2 phy config */
	70	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
	71
f2708c97	72	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
b44566c4 M	73	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
b44566c4 M	74
f2708c97	75	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
b44566c4 M	76	if (utmi_bits == 16) {
	77	reg \|= DWC3_GUSB2PHYCFG_PHYIF;
	78	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	79	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	80	} else if (utmi_bits == 8) {
	81	reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
	82	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	83	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
	84	}
	85
f2708c97	86	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
b44566c4 M	87	reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
b44566c4 M	88
f2708c97	89	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
b44566c4 M	90	reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
	91
	92	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
	93	}
	94
	95	static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
	96	struct udevice *dev)
	97	{
	98	int ret;
	99
	100	ret = dwc3_core_init(rkxhci->dwc3_reg);
	101	if (ret) {
9b643e31	102	pr_err("failed to initialize core\n");
b44566c4 M	103	return ret;
	104	}
	105
	106	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
	107
	108	/* We are hard-coding DWC3 core to Host Mode */
	109	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
	110
	111	return 0;
	112	}
	113
	114	static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
	115	{
	116	return 0;
	117	}
	118
	119	static int xhci_usb_probe(struct udevice *dev)
	120	{
	121	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
	122	struct rockchip_xhci *ctx = dev_get_priv(dev);
	123	struct xhci_hcor *hcor;
	124	int ret;
	125
	126	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
	127	ctx->dwc3_reg = (struct dwc3 )((char )(ctx->hcd) + DWC3_REG_OFFSET);
	128	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
	129	HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
	130
26a8b80f MD	131	if (plat->vbus_supply) {
	132	ret = regulator_set_enable(plat->vbus_supply, true);
	133	if (ret) {
9b643e31	134	pr_err("XHCI: failed to set VBus supply\n");
26a8b80f MD	135	return ret;
	136	}
	137	}
b44566c4 M	138
	139	ret = rockchip_xhci_core_init(ctx, dev);
	140	if (ret) {
9b643e31	141	pr_err("XHCI: failed to initialize controller\n");
b44566c4 M	142	return ret;
	143	}
	144
	145	return xhci_register(dev, ctx->hcd, hcor);
	146	}
	147
	148	static int xhci_usb_remove(struct udevice *dev)
	149	{
d3cb14b9	150	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
b44566c4 M	151	struct rockchip_xhci *ctx = dev_get_priv(dev);
	152	int ret;
	153
	154	ret = xhci_deregister(dev);
	155	if (ret)
	156	return ret;
	157	ret = rockchip_xhci_core_exit(ctx);
	158	if (ret)
	159	return ret;
	160
26a8b80f MD	161	if (plat->vbus_supply) {
	162	ret = regulator_set_enable(plat->vbus_supply, false);
	163	if (ret)
9b643e31	164	pr_err("XHCI: failed to set VBus supply\n");
26a8b80f	165	}
d3cb14b9	166
26a8b80f	167	return ret;
b44566c4 M	168	}
	169
	170	static const struct udevice_id xhci_usb_ids[] = {
d3cb14b9	171	{ .compatible = "rockchip,rk3328-xhci" },
b44566c4 M	172	{ }
	173	};
	174
	175	U_BOOT_DRIVER(usb_xhci) = {
	176	.name = "xhci_rockchip",
	177	.id = UCLASS_USB,
	178	.of_match = xhci_usb_ids,
	179	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
	180	.probe = xhci_usb_probe,
	181	.remove = xhci_usb_remove,
	182	.ops = &xhci_usb_ops,
	183	.bind = dm_scan_fdt_dev,
	184	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
	185	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
	186	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	187	};
	188
	189	static const struct udevice_id usb_phy_ids[] = {
d3cb14b9	190	{ .compatible = "rockchip,rk3328-usb3-phy" },
b44566c4 M	191	{ }
	192	};
	193
	194	U_BOOT_DRIVER(usb_phy) = {
	195	.name = "usb_phy_rockchip",
	196	.of_match = usb_phy_ids,
	197	};