[thirdparty/u-boot.git] / include / altera.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 */

#include <fpga.h>

#ifndef _ALTERA_H_
#define _ALTERA_H_

/*
 * For the StratixV FPGA programming via SPI, the following
 * information is coded in the 32bit cookie:
 * Bit 31 ... Bit 0
 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
 */
#define FPGA_COOKIE(bus, dev, config, done)			\
	(((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
#define COOKIE2SPI_BUS(c)	(((c) >> 24) & 0xff)
#define COOKIE2SPI_DEV(c)	(((c) >> 16) & 0xff)
#define COOKIE2CONFIG(c)	(((c) >> 8) & 0xff)
#define COOKIE2DONE(c)		((c) & 0xff)

enum altera_iface {
	/* insert all new types after this */
	min_altera_iface_type,
	/* serial data and external clock */
	passive_serial,
	/* parallel data */
	passive_parallel_synchronous,
	/* parallel data */
	passive_parallel_asynchronous,
	/* serial data w/ internal clock (not used) */
	passive_serial_asynchronous,
	/* jtag/tap serial (not used ) */
	altera_jtag_mode,
	/* fast passive parallel (FPP) */
	fast_passive_parallel,
	/* fast passive parallel with security (FPPS) */
	fast_passive_parallel_security,
	/* secure device manager (SDM) mailbox */
	secure_device_manager_mailbox,
	/* insert all new types before this */
	max_altera_iface_type,
};

enum altera_family {
	/* insert all new types after this */
	min_altera_type,
	/* ACEX1K Family */
	Altera_ACEX1K,
	/* CYCLONII Family */
	Altera_CYC2,
	/* StratixII Family */
	Altera_StratixII,
	/* StratixV Family */
	Altera_StratixV,
	/* Stratix10 Family */
	Intel_FPGA_Stratix10,
	/* SoCFPGA Family */
	Altera_SoCFPGA,

	/* Add new models here */

	/* insert all new types before this */
	max_altera_type,
};

typedef struct {
	/* part type */
	enum altera_family	family;
	/* interface type */
	enum altera_iface	iface;
	/* bytes of data part can accept */
	size_t			size;
	/* interface function table */
	void			*iface_fns;
	/* base interface address */
	void			*base;
	/* implementation specific cookie */
	int			cookie;
} Altera_desc;

/* Generic Altera Functions
 *********************************************************************/
extern int altera_load(Altera_desc *desc, const void *image, size_t size);
extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
extern int altera_info(Altera_desc *desc);

/* Board specific implementation specific function types
 *********************************************************************/
typedef int (*Altera_pre_fn)( int cookie );
typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
typedef int (*Altera_status_fn)( int cookie );
typedef int (*Altera_done_fn)( int cookie );
typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
typedef int (*Altera_abort_fn)( int cookie );
typedef int (*Altera_post_fn)( int cookie );

typedef struct {
	Altera_pre_fn pre;
	Altera_config_fn config;
	Altera_status_fn status;
	Altera_done_fn done;
	Altera_clk_fn clk;
	Altera_data_fn data;
	Altera_write_fn write;
	Altera_abort_fn abort;
	Altera_post_fn post;
} altera_board_specific_func;

#ifdef CONFIG_FPGA_SOCFPGA
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif

#ifdef CONFIG_FPGA_STRATIX_V
int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif

#ifdef CONFIG_FPGA_STRATIX10
int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
#endif

#endif /* _ALTERA_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c609719b WD	2	/*
	3	* (C) Copyright 2002
	4	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
c609719b WD	5	*/
	6
	7	#include <fpga.h>
	8
	9	#ifndef _ALTERA_H_
	10	#define _ALTERA_H_
	11
ff9c4c53 SR	12	/*
	13	* For the StratixV FPGA programming via SPI, the following
	14	* information is coded in the 32bit cookie:
	15	* Bit 31 ... Bit 0
	16	* SPI-Bus \| SPI-Dev \| Config-Pin \| Done-Pin
	17	*/
	18	#define FPGA_COOKIE(bus, dev, config, done) \
	19	(((bus) << 24) \| ((dev) << 16) \| ((config) << 8) \| (done))
	20	#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff)
	21	#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff)
	22	#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff)
	23	#define COOKIE2DONE(c) ((c) & 0xff)
	24
d44ef7ff MV	25	enum altera_iface {
	26	/* insert all new types after this */
	27	min_altera_iface_type,
	28	/* serial data and external clock */
	29	passive_serial,
	30	/* parallel data */
	31	passive_parallel_synchronous,
	32	/* parallel data */
	33	passive_parallel_asynchronous,
	34	/* serial data w/ internal clock (not used) */
	35	passive_serial_asynchronous,
	36	/* jtag/tap serial (not used ) */
	37	altera_jtag_mode,
	38	/* fast passive parallel (FPP) */
	39	fast_passive_parallel,
	40	/* fast passive parallel with security (FPPS) */
	41	fast_passive_parallel_security,
877ec6eb ACH	42	/* secure device manager (SDM) mailbox */
877ec6eb ACH	43	secure_device_manager_mailbox,
d44ef7ff MV	44	/* insert all new types before this */
	45	max_altera_iface_type,
	46	};
	47
	48	enum altera_family {
	49	/* insert all new types after this */
	50	min_altera_type,
	51	/* ACEX1K Family */
	52	Altera_ACEX1K,
	53	/* CYCLONII Family */
	54	Altera_CYC2,
	55	/* StratixII Family */
	56	Altera_StratixII,
ff9c4c53 SR	57	/* StratixV Family */
ff9c4c53 SR	58	Altera_StratixV,
877ec6eb ACH	59	/* Stratix10 Family */
877ec6eb ACH	60	Intel_FPGA_Stratix10,
230fe9b2 PM	61	/* SoCFPGA Family */
230fe9b2 PM	62	Altera_SoCFPGA,
d44ef7ff MV	63
	64	/* Add new models here */
	65
	66	/* insert all new types before this */
	67	max_altera_type,
	68	};
	69
	70	typedef struct {
	71	/* part type */
	72	enum altera_family family;
	73	/* interface type */
	74	enum altera_iface iface;
	75	/* bytes of data part can accept */
	76	size_t size;
	77	/* interface function table */
	78	void *iface_fns;
	79	/* base interface address */
	80	void *base;
	81	/* implementation specific cookie */
	82	int cookie;
	83	} Altera_desc;
c609719b	84
5da627a4 WD	85	/* Generic Altera Functions
5da627a4 WD	86	*********************************************************************/
e6a857da WD	87	extern int altera_load(Altera_desc desc, const void image, size_t size);
	88	extern int altera_dump(Altera_desc desc, const void buf, size_t bsize);
	89	extern int altera_info(Altera_desc *desc);
5da627a4 WD	90
	91	/* Board specific implementation specific function types
	92	*********************************************************************/
	93	typedef int (*Altera_pre_fn)( int cookie );
	94	typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
	95	typedef int (*Altera_status_fn)( int cookie );
	96	typedef int (*Altera_done_fn)( int cookie );
	97	typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
	98	typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
e6a857da	99	typedef int(Altera_write_fn)(const void buf, size_t len, int flush, int cookie);
5da627a4 WD	100	typedef int (*Altera_abort_fn)( int cookie );
5da627a4 WD	101	typedef int (*Altera_post_fn)( int cookie );
c609719b	102
3c735e74	103	typedef struct {
	104	Altera_pre_fn pre;
	105	Altera_config_fn config;
	106	Altera_status_fn status;
	107	Altera_done_fn done;
	108	Altera_clk_fn clk;
	109	Altera_data_fn data;
ff9c4c53	110	Altera_write_fn write;
3c735e74	111	Altera_abort_fn abort;
	112	Altera_post_fn post;
	113	} altera_board_specific_func;
	114
230fe9b2 PM	115	#ifdef CONFIG_FPGA_SOCFPGA
	116	int socfpga_load(Altera_desc desc, const void rbf_data, size_t rbf_size);
	117	#endif
	118
ff9c4c53 SR	119	#ifdef CONFIG_FPGA_STRATIX_V
	120	int stratixv_load(Altera_desc desc, const void rbf_data, size_t rbf_size);
	121	#endif
	122
c41e660b ACH	123	#ifdef CONFIG_FPGA_STRATIX10
	124	int stratix10_load(Altera_desc desc, const void rbf_data, size_t rbf_size);
	125	#endif
	126
5da627a4	127	#endif /* _ALTERA_H_ */