[thirdparty/u-boot.git] / include / fsl_ddr_dimm_params.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008-2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP Semiconductor
 */

#ifndef DDR2_DIMM_PARAMS_H
#define DDR2_DIMM_PARAMS_H

#define EDC_DATA_PARITY	1
#define EDC_ECC		2
#define EDC_AC_PARITY	4

/* Parameters for a DDR dimm computed from the SPD */
typedef struct dimm_params_s {

	/* DIMM organization parameters */
	char mpart[19];		/* guaranteed null terminated */

	unsigned int n_ranks;
	unsigned int die_density;
	unsigned long long rank_density;
	unsigned long long capacity;
	unsigned int data_width;
	unsigned int primary_sdram_width;
	unsigned int ec_sdram_width;
	unsigned int registered_dimm;
	unsigned int package_3ds;	/* number of dies in 3DS DIMM */
	unsigned int device_width;	/* x4, x8, x16 components */

	/* SDRAM device parameters */
	unsigned int n_row_addr;
	unsigned int n_col_addr;
	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int bank_addr_bits;
	unsigned int bank_group_bits;
#else
	unsigned int n_banks_per_sdram_device;
#endif
	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */

	/* used in computing base address of DIMMs */
	unsigned long long base_address;
	/* mirrored DIMMs */
	unsigned int mirrored_dimm;	/* only for ddr3 */

	/* DIMM timing parameters */

	int mtb_ps;	/* medium timebase ps */
	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
	int taa_ps;	/* minimum CAS latency time */
	int tfaw_ps;	/* four active window delay */

	/*
	 * SDRAM clock periods
	 * The range for these are 1000-10000 so a short should be sufficient
	 */
	int tckmin_x_ps;
	int tckmin_x_minus_1_ps;
	int tckmin_x_minus_2_ps;
	int tckmax_ps;

	/* SPD-defined CAS latencies */
	unsigned int caslat_x;
	unsigned int caslat_x_minus_1;
	unsigned int caslat_x_minus_2;

	unsigned int caslat_lowest_derated;	/* Derated CAS latency */

	/* basic timing parameters */
	int trcd_ps;
	int trp_ps;
	int tras_ps;

#ifdef CONFIG_SYS_FSL_DDR4
	int trfc1_ps;
	int trfc2_ps;
	int trfc4_ps;
	int trrds_ps;
	int trrdl_ps;
	int tccdl_ps;
	int trfc_slr_ps;
#else
	int twr_ps;	/* maximum = 63750 ps */
	int trfc_ps;	/* max = 255 ns + 256 ns + .75 ns
				       = 511750 ps */
	int trrd_ps;	/* maximum = 63750 ps */
	int twtr_ps;	/* maximum = 63750 ps */
	int trtp_ps;	/* byte 38, spd->trtp */
#endif

	int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */

	int refresh_rate_ps;
	int extended_op_srt;

#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
	int tis_ps;	/* byte 32, spd->ca_setup */
	int tih_ps;	/* byte 33, spd->ca_hold */
	int tds_ps;	/* byte 34, spd->data_setup */
	int tdh_ps;	/* byte 35, spd->data_hold */
	int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
	int tqhs_ps;	/* byte 45, spd->tqhs */
#endif

	/* DDR3 & DDR4 RDIMM */
	unsigned char rcw[16];	/* Register Control Word 0-15 */
#ifdef CONFIG_SYS_FSL_DDR4
	unsigned int dq_mapping[18];
	unsigned int dq_mapping_ors;
#endif
} dimm_params_t;

unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
					 const generic_spd_eeprom_t *spd,
					 dimm_params_t *pdimm,
					 unsigned int dimm_number);

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
58e5e9af	2	/*
c0c32af0 YS	3	* Copyright 2008-2016 Freescale Semiconductor, Inc.
c0c32af0 YS	4	* Copyright 2017-2018 NXP Semiconductor
58e5e9af KG	5	*/
	6
	7	#ifndef DDR2_DIMM_PARAMS_H
	8	#define DDR2_DIMM_PARAMS_H
	9
08b3f759 YS	10	#define EDC_DATA_PARITY 1
	11	#define EDC_ECC 2
	12	#define EDC_AC_PARITY 4
	13
34e026f9	14	/* Parameters for a DDR dimm computed from the SPD */
58e5e9af KG	15	typedef struct dimm_params_s {
	16
	17	/* DIMM organization parameters */
	18	char mpart[19]; /* guaranteed null terminated */
	19
	20	unsigned int n_ranks;
c0c32af0	21	unsigned int die_density;
58e5e9af KG	22	unsigned long long rank_density;
	23	unsigned long long capacity;
	24	unsigned int data_width;
	25	unsigned int primary_sdram_width;
	26	unsigned int ec_sdram_width;
	27	unsigned int registered_dimm;
c0c32af0	28	unsigned int package_3ds; /* number of dies in 3DS DIMM */
b61e0615	29	unsigned int device_width; /* x4, x8, x16 components */
58e5e9af KG	30
	31	/* SDRAM device parameters */
	32	unsigned int n_row_addr;
	33	unsigned int n_col_addr;
	34	unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
34e026f9 YS	35	#ifdef CONFIG_SYS_FSL_DDR4
	36	unsigned int bank_addr_bits;
	37	unsigned int bank_group_bits;
	38	#else
58e5e9af	39	unsigned int n_banks_per_sdram_device;
34e026f9	40	#endif
58e5e9af	41	unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
58e5e9af KG	42
	43	/* used in computing base address of DIMMs */
	44	unsigned long long base_address;
c360ceac DL	45	/* mirrored DIMMs */
c360ceac DL	46	unsigned int mirrored_dimm; /* only for ddr3 */
58e5e9af KG	47
	48	/* DIMM timing parameters */
	49
34e026f9 YS	50	int mtb_ps; /* medium timebase ps */
	51	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
	52	int taa_ps; /* minimum CAS latency time */
	53	int tfaw_ps; /* four active window delay */
c360ceac	54
58e5e9af KG	55	/*
	56	* SDRAM clock periods
	57	* The range for these are 1000-10000 so a short should be sufficient
	58	*/
34e026f9 YS	59	int tckmin_x_ps;
	60	int tckmin_x_minus_1_ps;
	61	int tckmin_x_minus_2_ps;
	62	int tckmax_ps;
58e5e9af KG	63
58e5e9af KG	64	/* SPD-defined CAS latencies */
0dd38a35 PJ	65	unsigned int caslat_x;
	66	unsigned int caslat_x_minus_1;
	67	unsigned int caslat_x_minus_2;
58e5e9af KG	68
	69	unsigned int caslat_lowest_derated; /* Derated CAS latency */
	70
	71	/* basic timing parameters */
34e026f9 YS	72	int trcd_ps;
	73	int trp_ps;
	74	int tras_ps;
	75
	76	#ifdef CONFIG_SYS_FSL_DDR4
	77	int trfc1_ps;
	78	int trfc2_ps;
	79	int trfc4_ps;
	80	int trrds_ps;
	81	int trrdl_ps;
	82	int tccdl_ps;
c0c32af0	83	int trfc_slr_ps;
34e026f9 YS	84	#else
	85	int twr_ps; /* maximum = 63750 ps */
	86	int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
58e5e9af	87	= 511750 ps */
34e026f9 YS	88	int trrd_ps; /* maximum = 63750 ps */
	89	int twtr_ps; /* maximum = 63750 ps */
	90	int trtp_ps; /* byte 38, spd->trtp */
	91	#endif
58e5e9af	92
34e026f9	93	int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
58e5e9af	94
34e026f9 YS	95	int refresh_rate_ps;
34e026f9 YS	96	int extended_op_srt;
58e5e9af	97
34e026f9 YS	98	#if defined(CONFIG_SYS_FSL_DDR1) \|\| defined(CONFIG_SYS_FSL_DDR2)
	99	int tis_ps; /* byte 32, spd->ca_setup */
	100	int tih_ps; /* byte 33, spd->ca_hold */
	101	int tds_ps; /* byte 34, spd->data_setup */
	102	int tdh_ps; /* byte 35, spd->data_hold */
	103	int tdqsq_max_ps; /* byte 44, spd->tdqsq */
	104	int tqhs_ps; /* byte 45, spd->tqhs */
	105	#endif
9490ff48	106
564e9383	107	/* DDR3 & DDR4 RDIMM */
9490ff48	108	unsigned char rcw[16]; /* Register Control Word 0-15 */
34e026f9 YS	109	#ifdef CONFIG_SYS_FSL_DDR4
	110	unsigned int dq_mapping[18];
	111	unsigned int dq_mapping_ors;
	112	#endif
58e5e9af KG	113	} dimm_params_t;
58e5e9af KG	114
03e664d8	115	unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
58e5e9af KG	116	const generic_spd_eeprom_t *spd,
	117	dimm_params_t *pdimm,
	118	unsigned int dimm_number);
	119
	120	#endif