]> git.ipfire.org Git - thirdparty/u-boot.git/blame - include/pch.h
Merge tag 'u-boot-rockchip-20190819' of https://gitlab.denx.de/u-boot/custodians...
[thirdparty/u-boot.git] / include / pch.h
CommitLineData
83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
ca831f49
SG
2/*
3 * Copyright (c) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
ca831f49
SG
5 */
6
7#ifndef __pch_h
8#define __pch_h
9
1ff4f321
SG
10#define PCH_RCBA 0xf0
11
12#define BIOS_CTRL_BIOSWE BIT(0)
13
1260f8c0
SG
14/* All the supported PCH ioctls */
15enum pch_req_t {
67b0cda7
SG
16 /* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
17 PCH_REQ_HDA_CONFIG,
18
b69b603b
SG
19 /* Fills out a struct pch_pmbase_info if available */
20 PCH_REQ_PMBASE_INFO,
21
1260f8c0
SG
22 PCH_REQ_TEST1, /* Test requests for sandbox driver */
23 PCH_REQ_TEST2,
24 PCH_REQ_TEST3,
25
26 PCH_REQ_COUNT, /* Number of ioctrls supported */
27};
28
b69b603b
SG
29/**
30 * struct pch_pmbase_info - Information filled in by PCH_REQ_PMBASE_INFO
31 *
32 * @pmbase: IO address of power-management controller
33 * @gpio0_en_ofs: Offset of GPIO0 enable register
34 * @pm1_sts_ofs: Offset of status register
35 * @pm1_cnt_ofs: Offset of control register
36 */
37struct pch_pmbase_info {
38 u16 base;
39 u8 gpio0_en_ofs;
40 u8 pm1_sts_ofs;
41 u8 pm1_cnt_ofs;
42};
43
1260f8c0
SG
44/**
45 * struct pch_ops - Operations for the Platform Controller Hub
46 *
47 * Consider using ioctl() to add rarely used or driver-specific operations.
48 */
ca831f49
SG
49struct pch_ops {
50 /**
3e389d8b 51 * get_spi_base() - get the address of SPI base
ca831f49
SG
52 *
53 * @dev: PCH device to check
54 * @sbasep: Returns address of SPI base if available, else 0
55 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
56 */
3e389d8b 57 int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
ca831f49 58
ca831f49
SG
59 /**
60 * set_spi_protect() - set whether SPI flash is protected or not
61 *
62 * @dev: PCH device to adjust
63 * @protect: true to protect, false to unprotect
64 *
65 * @return 0 on success, -ENOSYS if not implemented
66 */
67 int (*set_spi_protect)(struct udevice *dev, bool protect);
384980c6
BM
68
69 /**
70 * get_gpio_base() - get the address of GPIO base
71 *
72 * @dev: PCH device to check
73 * @gbasep: Returns address of GPIO base if available, else 0
74 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
75 */
76 int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
79d4eb62
BM
77
78 /**
79 * get_io_base() - get the address of IO base
80 *
81 * @dev: PCH device to check
82 * @iobasep: Returns address of IO base if available, else 0
83 * @return 0 if OK, -ve on error (e.g. there is no IO base)
84 */
85 int (*get_io_base)(struct udevice *dev, u32 *iobasep);
1260f8c0
SG
86
87 /**
88 * ioctl() - perform misc read/write operations
89 *
90 * This is a catch-all operation intended to avoid adding lots of
91 * methods to this uclass, of which few are commonly used. Uncommon
92 * operations that pertain only to a few devices in this uclass should
93 * use this method instead of adding new methods.
94 *
95 * @dev: PCH device to check
96 * @req: PCH request ID
97 * @data: Input/output data
98 * @size: Size of input data (and maximum size of output data)
99 * @return size of output data on sucesss, -ve on error
100 */
101 int (*ioctl)(struct udevice *dev, enum pch_req_t req, void *data,
102 int size);
ca831f49
SG
103};
104
105#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
106
107/**
3e389d8b 108 * pch_get_spi_base() - get the address of SPI base
ca831f49
SG
109 *
110 * @dev: PCH device to check
111 * @sbasep: Returns address of SPI base if available, else 0
112 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
113 */
3e389d8b 114int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
ca831f49 115
ca831f49
SG
116/**
117 * set_spi_protect() - set whether SPI flash is protected or not
118 *
119 * @dev: PCH device to adjust
120 * @protect: true to protect, false to unprotect
121 *
122 * @return 0 on success, -ENOSYS if not implemented
123 */
124int pch_set_spi_protect(struct udevice *dev, bool protect);
125
384980c6
BM
126/**
127 * pch_get_gpio_base() - get the address of GPIO base
128 *
129 * @dev: PCH device to check
130 * @gbasep: Returns address of GPIO base if available, else 0
131 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
132 */
133int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
134
79d4eb62
BM
135/**
136 * pch_get_io_base() - get the address of IO base
137 *
138 * @dev: PCH device to check
139 * @iobasep: Returns address of IO base if available, else 0
140 * @return 0 if OK, -ve on error (e.g. there is no IO base)
141 */
142int pch_get_io_base(struct udevice *dev, u32 *iobasep);
143
1260f8c0
SG
144/**
145 * pch_ioctl() - perform misc read/write operations
146 *
147 * This is a catch-all operation intended to avoid adding lots of
148 * methods to this uclass, of which few are commonly used. Uncommon
149 * operations that pertain only to a few devices in this uclass should
150 * use this method instead of adding new methods.
151 *
152 * @dev: PCH device to check
153 * @req: PCH request ID
154 * @data: Input/output data
155 * @size: Size of input data (and maximum size of output data)
156 * @return size of output data on sucesss, -ve on error
157 */
158int pch_ioctl(struct udevice *dev, ulong req, void *data, int size);
159
ca831f49 160#endif