projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 928954fe PC |
2 | /* |
| 3 | * Copyright (C) STMicroelectronics SA 2017 | |
| 4 | * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics. | |
| 928954fe PC |
5 | */ |
| 6 | ||
| 7 | #ifndef __STM32_RCC_H_ | |
| 8 | #define __STM32_RCC_H_ | |
| 9 | ||
| 10 | #define AHB_PSC_1 0 | |
| 11 | #define AHB_PSC_2 0x8 | |
| 12 | #define AHB_PSC_4 0x9 | |
| 13 | #define AHB_PSC_8 0xA | |
| 14 | #define AHB_PSC_16 0xB | |
| 15 | #define AHB_PSC_64 0xC | |
| 16 | #define AHB_PSC_128 0xD | |
| 17 | #define AHB_PSC_256 0xE | |
| 18 | #define AHB_PSC_512 0xF | |
| 19 | ||
| 20 | #define APB_PSC_1 0 | |
| 21 | #define APB_PSC_2 0x4 | |
| 22 | #define APB_PSC_4 0x5 | |
| 23 | #define APB_PSC_8 0x6 | |
| 24 | #define APB_PSC_16 0x7 | |
| 25 | ||
| 26 | struct pll_psc { | |
| 27 | u8 pll_m; | |
| 28 | u16 pll_n; | |
| 29 | u8 pll_p; | |
| 30 | u8 pll_q; | |
| 31 | u8 ahb_psc; | |
| 32 | u8 apb1_psc; | |
| 33 | u8 apb2_psc; | |
| 34 | }; | |
| 35 | ||
| 36 | struct stm32_clk_info { | |
| 37 | struct pll_psc sys_pll_psc; | |
| 38 | bool has_overdrive; | |
| 4e97e257 | 39 | bool v2; |
| 928954fe PC |
40 | }; |
| 41 | ||
| 42 | enum soc_family { | |
| 8b414645 PC |
43 | STM32F42X, |
| 44 | STM32F469, | |
| 928954fe | 45 | STM32F7, |
| d090cbab | 46 | STM32MP1, |
| 928954fe PC |
47 | }; |
| 48 | ||
| 61803a95 PC |
49 | enum apb { |
| 50 | APB1, | |
| 51 | APB2, | |
| 52 | }; | |
| 53 | ||
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54 | struct stm32_rcc_clk { |
| 55 | char *drv_name; | |
| 56 | enum soc_family soc; | |
| 57 | }; | |
| 58 | ||
| 014a953c PC |
59 | struct stm32_rcc_regs { |
| 60 | u32 cr; /* RCC clock control */ | |
| 61 | u32 pllcfgr; /* RCC PLL configuration */ | |
| 62 | u32 cfgr; /* RCC clock configuration */ | |
| 63 | u32 cir; /* RCC clock interrupt */ | |
| 64 | u32 ahb1rstr; /* RCC AHB1 peripheral reset */ | |
| 65 | u32 ahb2rstr; /* RCC AHB2 peripheral reset */ | |
| 66 | u32 ahb3rstr; /* RCC AHB3 peripheral reset */ | |
| 67 | u32 rsv0; | |
| 68 | u32 apb1rstr; /* RCC APB1 peripheral reset */ | |
| 69 | u32 apb2rstr; /* RCC APB2 peripheral reset */ | |
| 70 | u32 rsv1[2]; | |
| 71 | u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ | |
| 72 | u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ | |
| 73 | u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ | |
| 74 | u32 rsv2; | |
| 75 | u32 apb1enr; /* RCC APB1 peripheral clock enable */ | |
| 76 | u32 apb2enr; /* RCC APB2 peripheral clock enable */ | |
| 77 | u32 rsv3[2]; | |
| 78 | u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ | |
| 79 | u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ | |
| 80 | u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ | |
| 81 | u32 rsv4; | |
| 82 | u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ | |
| 83 | u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ | |
| 84 | u32 rsv5[2]; | |
| 85 | u32 bdcr; /* RCC Backup domain control */ | |
| 86 | u32 csr; /* RCC clock control & status */ | |
| 87 | u32 rsv6[2]; | |
| 88 | u32 sscgr; /* RCC spread spectrum clock generation */ | |
| 89 | u32 plli2scfgr; /* RCC PLLI2S configuration */ | |
| 90 | /* below registers are only available on STM32F46x and STM32F7 SoCs*/ | |
| 91 | u32 pllsaicfgr; /* PLLSAI configuration */ | |
| 92 | u32 dckcfgr; /* dedicated clocks configuration register */ | |
| 93 | /* Below registers are only available on STM32F7 SoCs */ | |
| 94 | u32 dckcfgr2; /* dedicated clocks configuration register */ | |
| 95 | }; | |
| 96 | ||
| 928954fe | 97 | #endif /* __STM32_RCC_H_ */ |