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83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
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2/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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5 */
6
7#include <fpga.h>
8
9#ifndef _XILINX_H_
10#define _XILINX_H_
11
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12/* Xilinx types
13 *********************************************************************/
2df9d5c4 14typedef enum { /* typedef xilinx_iface */
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15 min_xilinx_iface_type, /* low range check value */
16 slave_serial, /* serial data and external clock */
17 master_serial, /* serial data w/ internal clock (not used) */
18 slave_parallel, /* parallel data w/ external latch */
19 jtag_mode, /* jtag/tap serial (not used ) */
20 master_selectmap, /* master SelectMap (virtex2) */
21 slave_selectmap, /* slave SelectMap (virtex2) */
d5dae85f 22 devcfg, /* devcfg interface (zynq) */
6b245014 23 csu_dma, /* csu_dma interface (zynqmp) */
53677ef1 24 max_xilinx_iface_type /* insert all new types before this */
2df9d5c4 25} xilinx_iface; /* end, typedef xilinx_iface */
c609719b 26
2df9d5c4 27typedef enum { /* typedef xilinx_family */
53677ef1 28 min_xilinx_type, /* low range check value */
b625b9ae 29 xilinx_spartan2, /* Spartan-II Family */
2df9d5c4 30 xilinx_virtexE, /* Virtex-E Family */
d9071ce0 31 xilinx_virtex2, /* Virtex2 Family */
2a6e3869 32 xilinx_spartan3, /* Spartan-III Family */
d5dae85f 33 xilinx_zynq, /* Zynq Family */
6b245014 34 xilinx_zynqmp, /* ZynqMP Family */
53677ef1 35 max_xilinx_type /* insert all new types before this */
2df9d5c4 36} xilinx_family; /* end, typedef xilinx_family */
c609719b 37
f8c1be98 38typedef struct { /* typedef xilinx_desc */
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39 xilinx_family family; /* part type */
40 xilinx_iface iface; /* interface type */
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41 size_t size; /* bytes of data part can accept */
42 void *iface_fns; /* interface function table */
43 int cookie; /* implementation specific cookie */
14cfc4f3 44 struct xilinx_fpga_op *operations; /* operations */
6631db47 45 char *name; /* device name in bitstream */
f8c1be98 46} xilinx_desc; /* end, typedef xilinx_desc */
c609719b 47
14cfc4f3 48struct xilinx_fpga_op {
7a78bd26 49 int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
1a897668 50 int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
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51 int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize,
52 struct fpga_secure_info *fpga_sec_info);
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53 int (*dump)(xilinx_desc *, const void *, size_t);
54 int (*info)(xilinx_desc *);
55};
56
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57/* Generic Xilinx Functions
58 *********************************************************************/
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59int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
60 bitstream_type bstype);
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61int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
62int xilinx_info(xilinx_desc *desc);
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63int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
64 fpga_fs_info *fpga_fsinfo);
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65int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
66 struct fpga_secure_info *fpga_sec_info);
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67
68/* Board specific implementation specific function types
69 *********************************************************************/
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70typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
71typedef int (*xilinx_init_fn)(int cookie);
72typedef int (*xilinx_err_fn)(int cookie);
73typedef int (*xilinx_done_fn)(int cookie);
74typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
75typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
76typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
77typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
78typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
79typedef int (*xilinx_busy_fn)(int cookie);
80typedef int (*xilinx_abort_fn)(int cookie);
81typedef int (*xilinx_pre_fn)(int cookie);
82typedef int (*xilinx_post_fn)(int cookie);
83typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
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84
85#endif /* _XILINX_H_ */