[thirdparty/u-boot.git] / include / zynqmppl.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * (C) Copyright 2015 Xilinx, Inc,
 * Michal Simek <michal.simek@xilinx.com>
 */

#ifndef _ZYNQMPPL_H_
#define _ZYNQMPPL_H_

#include <xilinx.h>

#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS		0xC2000017
#define ZYNQMP_FPGA_OP_INIT			(1 << 0)
#define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
#define ZYNQMP_FPGA_OP_DONE			(1 << 2)

#define ZYNQMP_FPGA_FLAG_AUTHENTICATED		BIT(2)
#define ZYNQMP_FPGA_FLAG_ENCRYPTED		BIT(3)

#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xf << \
					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT	12
#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)

extern struct xilinx_fpga_op zynqmp_op;

#define XILINX_ZYNQMP_DESC \
{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }

#endif /* _ZYNQMPPL_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
6b245014 SDPP	2	/*
	3	* (C) Copyright 2015 Xilinx, Inc,
	4	* Michal Simek <michal.simek@xilinx.com>
6b245014 SDPP	5	*/
	6
	7	#ifndef _ZYNQMPPL_H_
	8	#define _ZYNQMPPL_H_
	9
	10	#include <xilinx.h>
	11
47e60cbd	12	#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
6b245014	13	#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
b32e11a7	14	#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017
6b245014 SDPP	15	#define ZYNQMP_FPGA_OP_INIT (1 << 0)
	16	#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
	17	#define ZYNQMP_FPGA_OP_DONE (1 << 2)
	18
a18d09ea SDPP	19	#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
	20	#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
	21
0cba6abb SB	22	#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
	23	#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
	24	ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
	25	#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
92687047	26	#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
0cba6abb	27
6b245014 SDPP	28	extern struct xilinx_fpga_op zynqmp_op;
	29
	30	#define XILINX_ZYNQMP_DESC \
	31	{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
	32
	33	#endif /* _ZYNQMPPL_H_ */