[thirdparty/u-boot.git] / tools / kwbimage.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2008
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 */

#ifndef _KWBIMAGE_H_
#define _KWBIMAGE_H_

#include <compiler.h>
#include <stdint.h>

#define KWBIMAGE_MAX_CONFIG	((0x1dc - 0x20)/sizeof(struct reg_config))
#define MAX_TEMPBUF_LEN		32

/* NAND ECC Mode */
#define IBR_HDR_ECC_DEFAULT		0x00
#define IBR_HDR_ECC_FORCED_HAMMING	0x01
#define IBR_HDR_ECC_FORCED_RS  		0x02
#define IBR_HDR_ECC_DISABLED  		0x03

/* Boot Type - block ID */
#define IBR_HDR_I2C_ID			0x4D
#define IBR_HDR_SPI_ID			0x5A
#define IBR_HDR_NAND_ID			0x8B
#define IBR_HDR_SATA_ID			0x78
#define IBR_HDR_PEX_ID			0x9C
#define IBR_HDR_UART_ID			0x69
#define IBR_DEF_ATTRIB	 		0x00

#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))

/* Structure of the main header, version 0 (Kirkwood, Dove) */
struct main_hdr_v0 {
	uint8_t  blockid;		/* 0x0       */
	uint8_t  nandeccmode;		/* 0x1       */
	uint16_t nandpagesize;		/* 0x2-0x3   */
	uint32_t blocksize;		/* 0x4-0x7   */
	uint32_t rsvd1;			/* 0x8-0xB   */
	uint32_t srcaddr;		/* 0xC-0xF   */
	uint32_t destaddr;		/* 0x10-0x13 */
	uint32_t execaddr;		/* 0x14-0x17 */
	uint8_t  satapiomode;		/* 0x18      */
	uint8_t  rsvd3;			/* 0x19      */
	uint16_t ddrinitdelay;		/* 0x1A-0x1B */
	uint16_t rsvd2;			/* 0x1C-0x1D */
	uint8_t  ext;			/* 0x1E      */
	uint8_t  checksum;		/* 0x1F      */
};

struct ext_hdr_v0_reg {
	uint32_t raddr;
	uint32_t rdata;
};

#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))

struct ext_hdr_v0 {
	uint32_t              offset;
	uint8_t               reserved[0x20 - sizeof(uint32_t)];
	struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
	uint8_t               reserved2[7];
	uint8_t               checksum;
};

struct kwb_header {
	struct main_hdr_v0	kwb_hdr;
	struct ext_hdr_v0	kwb_exthdr;
};

/* Structure of the main header, version 1 (Armada 370/38x/XP) */
struct main_hdr_v1 {
	uint8_t  blockid;               /* 0x0       */
	uint8_t  flags;                 /* 0x1       */
	uint16_t reserved2;             /* 0x2-0x3   */
	uint32_t blocksize;             /* 0x4-0x7   */
	uint8_t  version;               /* 0x8       */
	uint8_t  headersz_msb;          /* 0x9       */
	uint16_t headersz_lsb;          /* 0xA-0xB   */
	uint32_t srcaddr;               /* 0xC-0xF   */
	uint32_t destaddr;              /* 0x10-0x13 */
	uint32_t execaddr;              /* 0x14-0x17 */
	uint8_t  options;               /* 0x18      */
	uint8_t  nandblocksize;         /* 0x19      */
	uint8_t  nandbadblklocation;    /* 0x1A      */
	uint8_t  reserved4;             /* 0x1B      */
	uint16_t reserved5;             /* 0x1C-0x1D */
	uint8_t  ext;                   /* 0x1E      */
	uint8_t  checksum;              /* 0x1F      */
};

/*
 * Main header options
 */
#define MAIN_HDR_V1_OPT_BAUD_DEFAULT	0
#define MAIN_HDR_V1_OPT_BAUD_2400	0x1
#define MAIN_HDR_V1_OPT_BAUD_4800	0x2
#define MAIN_HDR_V1_OPT_BAUD_9600	0x3
#define MAIN_HDR_V1_OPT_BAUD_19200	0x4
#define MAIN_HDR_V1_OPT_BAUD_38400	0x5
#define MAIN_HDR_V1_OPT_BAUD_57600	0x6
#define MAIN_HDR_V1_OPT_BAUD_115200	0x7

/*
 * Header for the optional headers, version 1 (Armada 370, Armada XP)
 */
struct opt_hdr_v1 {
	uint8_t  headertype;
	uint8_t  headersz_msb;
	uint16_t headersz_lsb;
	char     data[0];
};

/*
 * Public Key data in DER format
 */
struct pubkey_der_v1 {
	uint8_t key[524];
};

/*
 * Signature (RSA 2048)
 */
struct sig_v1 {
	uint8_t sig[256];
};

/*
 * Structure of secure header (Armada 38x)
 */
struct secure_hdr_v1 {
	uint8_t  headertype;		/* 0x0 */
	uint8_t  headersz_msb;		/* 0x1 */
	uint16_t headersz_lsb;		/* 0x2 - 0x3 */
	uint32_t reserved1;		/* 0x4 - 0x7 */
	struct pubkey_der_v1 kak;	/* 0x8 - 0x213 */
	uint8_t  jtag_delay;		/* 0x214 */
	uint8_t  reserved2;		/* 0x215 */
	uint16_t reserved3;		/* 0x216 - 0x217 */
	uint32_t boxid;			/* 0x218 - 0x21B */
	uint32_t flashid;		/* 0x21C - 0x21F */
	struct sig_v1 hdrsig;		/* 0x220 - 0x31F */
	struct sig_v1 imgsig;		/* 0x320 - 0x41F */
	struct pubkey_der_v1 csk[16];	/* 0x420 - 0x24DF */
	struct sig_v1 csksig;		/* 0x24E0 - 0x25DF */
	uint8_t  next;			/* 0x25E0 */
	uint8_t  reserved4;		/* 0x25E1 */
	uint16_t reserved5;		/* 0x25E2 - 0x25E3 */
};

/*
 * Various values for the opt_hdr_v1->headertype field, describing the
 * different types of optional headers. The "secure" header contains
 * informations related to secure boot (encryption keys, etc.). The
 * "binary" header contains ARM binary code to be executed prior to
 * executing the main payload (usually the bootloader). This is
 * typically used to execute DDR3 training code. The "register" header
 * allows to describe a set of (address, value) tuples that are
 * generally used to configure the DRAM controller.
 */
#define OPT_HDR_V1_SECURE_TYPE   0x1
#define OPT_HDR_V1_BINARY_TYPE   0x2
#define OPT_HDR_V1_REGISTER_TYPE 0x3

#define KWBHEADER_V1_SIZE(hdr) \
	(((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))

enum kwbimage_cmd {
	CMD_INVALID,
	CMD_BOOT_FROM,
	CMD_NAND_ECC_MODE,
	CMD_NAND_PAGE_SIZE,
	CMD_SATA_PIO_MODE,
	CMD_DDR_INIT_DELAY,
	CMD_DATA
};

enum kwbimage_cmd_types {
	CFG_INVALID = -1,
	CFG_COMMAND,
	CFG_DATA0,
	CFG_DATA1
};

/*
 * functions
 */
void init_kwb_image_type (void);

/*
 * Byte 8 of the image header contains the version number. In the v0
 * header, byte 8 was reserved, and always set to 0. In the v1 header,
 * byte 8 has been changed to a proper field, set to 1.
 */
static inline unsigned int image_version(void *header)
{
	unsigned char *ptr = header;
	return ptr[8];
}

#endif /* _KWBIMAGE_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
aa0c7a86 PW	2	/*
	3	* (C) Copyright 2008
	4	* Marvell Semiconductor <www.marvell.com>
	5	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
aa0c7a86 PW	6	*/
	7
	8	#ifndef _KWBIMAGE_H_
	9	#define _KWBIMAGE_H_
	10
a8840dce	11	#include <compiler.h>
aa0c7a86 PW	12	#include <stdint.h>
	13
	14	#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
	15	#define MAX_TEMPBUF_LEN 32
	16
	17	/* NAND ECC Mode */
	18	#define IBR_HDR_ECC_DEFAULT 0x00
	19	#define IBR_HDR_ECC_FORCED_HAMMING 0x01
	20	#define IBR_HDR_ECC_FORCED_RS 0x02
	21	#define IBR_HDR_ECC_DISABLED 0x03
	22
	23	/* Boot Type - block ID */
	24	#define IBR_HDR_I2C_ID 0x4D
	25	#define IBR_HDR_SPI_ID 0x5A
	26	#define IBR_HDR_NAND_ID 0x8B
	27	#define IBR_HDR_SATA_ID 0x78
	28	#define IBR_HDR_PEX_ID 0x9C
	29	#define IBR_HDR_UART_ID 0x69
	30	#define IBR_DEF_ATTRIB 0x00
	31
e29f1db3	32	#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
aa0c7a86	33
e29f1db3 SR	34	/* Structure of the main header, version 0 (Kirkwood, Dove) */
e29f1db3 SR	35	struct main_hdr_v0 {
37d108b6 BS	36	uint8_t blockid; /* 0x0 */
	37	uint8_t nandeccmode; /* 0x1 */
	38	uint16_t nandpagesize; /* 0x2-0x3 */
	39	uint32_t blocksize; /* 0x4-0x7 */
	40	uint32_t rsvd1; /* 0x8-0xB */
	41	uint32_t srcaddr; /* 0xC-0xF */
	42	uint32_t destaddr; /* 0x10-0x13 */
	43	uint32_t execaddr; /* 0x14-0x17 */
	44	uint8_t satapiomode; /* 0x18 */
	45	uint8_t rsvd3; /* 0x19 */
	46	uint16_t ddrinitdelay; /* 0x1A-0x1B */
	47	uint16_t rsvd2; /* 0x1C-0x1D */
	48	uint8_t ext; /* 0x1E */
	49	uint8_t checksum; /* 0x1F */
e29f1db3	50	};
aa0c7a86	51
e29f1db3	52	struct ext_hdr_v0_reg {
aa0c7a86 PW	53	uint32_t raddr;
	54	uint32_t rdata;
	55	};
	56
e29f1db3 SR	57	#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
	58
	59	struct ext_hdr_v0 {
	60	uint32_t offset;
	61	uint8_t reserved[0x20 - sizeof(uint32_t)];
	62	struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
	63	uint8_t reserved2[7];
	64	uint8_t checksum;
	65	};
aa0c7a86 PW	66
aa0c7a86 PW	67	struct kwb_header {
e29f1db3 SR	68	struct main_hdr_v0 kwb_hdr;
	69	struct ext_hdr_v0 kwb_exthdr;
	70	};
	71
ed72741d	72	/* Structure of the main header, version 1 (Armada 370/38x/XP) */
e29f1db3	73	struct main_hdr_v1 {
37d108b6 BS	74	uint8_t blockid; /* 0x0 */
	75	uint8_t flags; /* 0x1 */
	76	uint16_t reserved2; /* 0x2-0x3 */
	77	uint32_t blocksize; /* 0x4-0x7 */
	78	uint8_t version; /* 0x8 */
	79	uint8_t headersz_msb; /* 0x9 */
	80	uint16_t headersz_lsb; /* 0xA-0xB */
	81	uint32_t srcaddr; /* 0xC-0xF */
	82	uint32_t destaddr; /* 0x10-0x13 */
	83	uint32_t execaddr; /* 0x14-0x17 */
	84	uint8_t options; /* 0x18 */
	85	uint8_t nandblocksize; /* 0x19 */
	86	uint8_t nandbadblklocation; /* 0x1A */
	87	uint8_t reserved4; /* 0x1B */
	88	uint16_t reserved5; /* 0x1C-0x1D */
	89	uint8_t ext; /* 0x1E */
	90	uint8_t checksum; /* 0x1F */
e29f1db3 SR	91	};
e29f1db3 SR	92
4bdb5479 CP	93	/*
	94	* Main header options
	95	*/
	96	#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
	97	#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
	98	#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
	99	#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
	100	#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
	101	#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
	102	#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
	103	#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
	104
e29f1db3 SR	105	/*
	106	* Header for the optional headers, version 1 (Armada 370, Armada XP)
	107	*/
	108	struct opt_hdr_v1 {
	109	uint8_t headertype;
	110	uint8_t headersz_msb;
	111	uint16_t headersz_lsb;
	112	char data[0];
	113	};
	114
a1b6b0a9 MS	115	/*
	116	* Public Key data in DER format
	117	*/
	118	struct pubkey_der_v1 {
	119	uint8_t key[524];
	120	};
	121
	122	/*
	123	* Signature (RSA 2048)
	124	*/
	125	struct sig_v1 {
	126	uint8_t sig[256];
	127	};
	128
	129	/*
	130	* Structure of secure header (Armada 38x)
	131	*/
	132	struct secure_hdr_v1 {
	133	uint8_t headertype; /* 0x0 */
	134	uint8_t headersz_msb; /* 0x1 */
	135	uint16_t headersz_lsb; /* 0x2 - 0x3 */
	136	uint32_t reserved1; /* 0x4 - 0x7 */
	137	struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
	138	uint8_t jtag_delay; /* 0x214 */
	139	uint8_t reserved2; /* 0x215 */
	140	uint16_t reserved3; /* 0x216 - 0x217 */
	141	uint32_t boxid; /* 0x218 - 0x21B */
	142	uint32_t flashid; /* 0x21C - 0x21F */
	143	struct sig_v1 hdrsig; /* 0x220 - 0x31F */
	144	struct sig_v1 imgsig; /* 0x320 - 0x41F */
	145	struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
	146	struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
	147	uint8_t next; /* 0x25E0 */
	148	uint8_t reserved4; /* 0x25E1 */
	149	uint16_t reserved5; /* 0x25E2 - 0x25E3 */
	150	};
	151
e29f1db3 SR	152	/*
	153	* Various values for the opt_hdr_v1->headertype field, describing the
	154	* different types of optional headers. The "secure" header contains
	155	* informations related to secure boot (encryption keys, etc.). The
	156	* "binary" header contains ARM binary code to be executed prior to
	157	* executing the main payload (usually the bootloader). This is
	158	* typically used to execute DDR3 training code. The "register" header
	159	* allows to describe a set of (address, value) tuples that are
	160	* generally used to configure the DRAM controller.
	161	*/
	162	#define OPT_HDR_V1_SECURE_TYPE 0x1
	163	#define OPT_HDR_V1_BINARY_TYPE 0x2
	164	#define OPT_HDR_V1_REGISTER_TYPE 0x3
	165
	166	#define KWBHEADER_V1_SIZE(hdr) \
a8840dce	167	(((hdr)->headersz_msb << 16) \| le16_to_cpu((hdr)->headersz_lsb))
e29f1db3 SR	168
	169	enum kwbimage_cmd {
	170	CMD_INVALID,
	171	CMD_BOOT_FROM,
	172	CMD_NAND_ECC_MODE,
	173	CMD_NAND_PAGE_SIZE,
	174	CMD_SATA_PIO_MODE,
	175	CMD_DDR_INIT_DELAY,
	176	CMD_DATA
	177	};
	178
	179	enum kwbimage_cmd_types {
	180	CFG_INVALID = -1,
	181	CFG_COMMAND,
	182	CFG_DATA0,
	183	CFG_DATA1
aa0c7a86 PW	184	};
	185
	186	/*
	187	* functions
	188	*/
	189	void init_kwb_image_type (void);
	190
e29f1db3 SR	191	/*
	192	* Byte 8 of the image header contains the version number. In the v0
	193	* header, byte 8 was reserved, and always set to 0. In the v1 header,
	194	* byte 8 has been changed to a proper field, set to 1.
	195	*/
	196	static inline unsigned int image_version(void *header)
	197	{
	198	unsigned char *ptr = header;
	199	return ptr[8];
	200	}
	201
aa0c7a86	202	#endif /* _KWBIMAGE_H_ */