[thirdparty/u-boot.git] / tools / prelink-riscv.inc

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017 Andes Technology
 * Chih-Mao Chen <cmchen@andestech.com>
 *
 * Statically process runtime relocations on RISC-V ELF images
 * so that it can be directly executed when loaded at LMA
 * without fixup. Both RV32 and RV64 are supported.
 */

#define CONCAT_IMPL(x, y) x##y
#define CONCAT(x, y) CONCAT_IMPL(x, y)
#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)

#define prelink_nn      CONCAT(prelink, PRELINK_INC_BITS)
#define uintnn_t        CONCAT3(uint, PRELINK_INC_BITS, _t)
#define get_offset_nn   CONCAT(get_offset_, PRELINK_INC_BITS)
#define Elf_Ehdr        CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
#define Elf_Phdr        CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
#define Elf_Rela        CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
#define Elf_Sym         CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
#define Elf_Dyn         CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
#define Elf_Addr        CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
#define ELF_R_TYPE      CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
#define ELF_R_SYM       CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
#define lenn_to_cpu     CONCAT3(le, PRELINK_INC_BITS, _to_cpu)

static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
{
	Elf_Phdr *p;

	for (p = phdrs; p < phdrs + phnum; ++p)
		if (lenn_to_cpu(p->p_vaddr) <= addr && lenn_to_cpu(p->p_vaddr) + lenn_to_cpu(p->p_memsz) > addr)
			return data + lenn_to_cpu(p->p_offset) + (addr - lenn_to_cpu(p->p_vaddr));

	return NULL;
}

static void prelink_nn(void *data)
{
	Elf_Ehdr *ehdr = data;
	Elf_Phdr *p;
	Elf_Dyn *dyn;
	Elf_Rela *r;

	if (le16_to_cpu(ehdr->e_machine) != EM_RISCV)
		die("Machine type is not RISC-V");

	Elf_Phdr *phdrs = data + lenn_to_cpu(ehdr->e_phoff);

	Elf_Dyn *dyns = NULL;
	for (p = phdrs; p < phdrs + le16_to_cpu(ehdr->e_phnum); ++p) {
		if (le32_to_cpu(p->p_type) == PT_DYNAMIC) {
			dyns = data + lenn_to_cpu(p->p_offset);
			break;
		}
	}

	if (dyns == NULL)
		die("No dynamic section found");

	Elf_Rela *rela_dyn = NULL;
	size_t rela_count = 0;
	Elf_Sym *dynsym = NULL;
	for (dyn = dyns;; ++dyn) {
		if (lenn_to_cpu(dyn->d_tag) == DT_NULL)
			break;
		else if (lenn_to_cpu(dyn->d_tag) == DT_RELA)
			rela_dyn = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), + lenn_to_cpu(dyn->d_un.d_ptr));
		else if (lenn_to_cpu(dyn->d_tag) == DT_RELASZ)
		  rela_count = lenn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
		else if (lenn_to_cpu(dyn->d_tag) == DT_SYMTAB)
			dynsym = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), + lenn_to_cpu(dyn->d_un.d_ptr));

	}

	if (rela_dyn == NULL)
		die("No .rela.dyn found");

	if (dynsym == NULL)
		die("No .dynsym found");

	for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
		void* buf = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), lenn_to_cpu(r->r_offset));

		if (buf == NULL)
			continue;

		if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
			*((uintnn_t*) buf) = r->r_addend;
		else if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_32)
			*((uint32_t*) buf) = dynsym[ELF_R_SYM(lenn_to_cpu(r->r_info))].st_value;
		else if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_64)
			*((uint64_t*) buf) = dynsym[ELF_R_SYM(lenn_to_cpu(r->r_info))].st_value;
	}
}

#undef prelink_nn
#undef uintnn_t
#undef get_offset_nn
#undef Elf_Ehdr
#undef Elf_Phdr
#undef Elf_Rela
#undef Elf_Sym
#undef Elf_Dyn
#undef Elf_Addr
#undef ELF_R_TYPE
#undef ELF_R_SYM
#undef lenn_to_cpu

#undef CONCAT_IMPL
#undef CONCAT
#undef CONCAT3
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
42ac26f2 RC	2	/*
	3	* Copyright (C) 2017 Andes Technology
	4	* Chih-Mao Chen <cmchen@andestech.com>
	5	*
42ac26f2 RC	6	* Statically process runtime relocations on RISC-V ELF images
	7	* so that it can be directly executed when loaded at LMA
	8	* without fixup. Both RV32 and RV64 are supported.
	9	*/
	10
	11	#define CONCAT_IMPL(x, y) x##y
	12	#define CONCAT(x, y) CONCAT_IMPL(x, y)
	13	#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
	14
	15	#define prelink_nn CONCAT(prelink, PRELINK_INC_BITS)
	16	#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
	17	#define get_offset_nn CONCAT(get_offset_, PRELINK_INC_BITS)
	18	#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
	19	#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
	20	#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
	21	#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
	22	#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
	23	#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
	24	#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
	25	#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
e604410d	26	#define lenn_to_cpu CONCAT3(le, PRELINK_INC_BITS, _to_cpu)
42ac26f2 RC	27
	28	static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
	29	{
	30	Elf_Phdr *p;
	31
	32	for (p = phdrs; p < phdrs + phnum; ++p)
e604410d MC	33	if (lenn_to_cpu(p->p_vaddr) <= addr && lenn_to_cpu(p->p_vaddr) + lenn_to_cpu(p->p_memsz) > addr)
e604410d MC	34	return data + lenn_to_cpu(p->p_offset) + (addr - lenn_to_cpu(p->p_vaddr));
42ac26f2 RC	35
	36	return NULL;
	37	}
	38
	39	static void prelink_nn(void *data)
	40	{
	41	Elf_Ehdr *ehdr = data;
	42	Elf_Phdr *p;
	43	Elf_Dyn *dyn;
	44	Elf_Rela *r;
	45
e604410d	46	if (le16_to_cpu(ehdr->e_machine) != EM_RISCV)
42ac26f2 RC	47	die("Machine type is not RISC-V");
42ac26f2 RC	48
e604410d	49	Elf_Phdr *phdrs = data + lenn_to_cpu(ehdr->e_phoff);
42ac26f2 RC	50
42ac26f2 RC	51	Elf_Dyn *dyns = NULL;
e604410d MC	52	for (p = phdrs; p < phdrs + le16_to_cpu(ehdr->e_phnum); ++p) {
	53	if (le32_to_cpu(p->p_type) == PT_DYNAMIC) {
	54	dyns = data + lenn_to_cpu(p->p_offset);
42ac26f2 RC	55	break;
	56	}
	57	}
	58
	59	if (dyns == NULL)
	60	die("No dynamic section found");
	61
	62	Elf_Rela *rela_dyn = NULL;
	63	size_t rela_count = 0;
	64	Elf_Sym *dynsym = NULL;
	65	for (dyn = dyns;; ++dyn) {
e604410d	66	if (lenn_to_cpu(dyn->d_tag) == DT_NULL)
42ac26f2	67	break;
e604410d MC	68	else if (lenn_to_cpu(dyn->d_tag) == DT_RELA)
	69	rela_dyn = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), + lenn_to_cpu(dyn->d_un.d_ptr));
	70	else if (lenn_to_cpu(dyn->d_tag) == DT_RELASZ)
	71	rela_count = lenn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
	72	else if (lenn_to_cpu(dyn->d_tag) == DT_SYMTAB)
	73	dynsym = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), + lenn_to_cpu(dyn->d_un.d_ptr));
42ac26f2 RC	74
	75	}
	76
	77	if (rela_dyn == NULL)
	78	die("No .rela.dyn found");
	79
	80	if (dynsym == NULL)
	81	die("No .dynsym found");
	82
	83	for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
e604410d	84	void* buf = get_offset_nn(data, phdrs, le16_to_cpu(ehdr->e_phnum), lenn_to_cpu(r->r_offset));
42ac26f2 RC	85
	86	if (buf == NULL)
	87	continue;
	88
e604410d	89	if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
42ac26f2	90	((uintnn_t) buf) = r->r_addend;
e604410d MC	91	else if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_32)
	92	((uint32_t) buf) = dynsym[ELF_R_SYM(lenn_to_cpu(r->r_info))].st_value;
	93	else if (ELF_R_TYPE(lenn_to_cpu(r->r_info)) == R_RISCV_64)
	94	((uint64_t) buf) = dynsym[ELF_R_SYM(lenn_to_cpu(r->r_info))].st_value;
42ac26f2 RC	95	}
	96	}
	97
	98	#undef prelink_nn
	99	#undef uintnn_t
	100	#undef get_offset_nn
	101	#undef Elf_Ehdr
	102	#undef Elf_Phdr
	103	#undef Elf_Rela
	104	#undef Elf_Sym
	105	#undef Elf_Dyn
	106	#undef Elf_Addr
	107	#undef ELF_R_TYPE
	108	#undef ELF_R_SYM
e604410d	109	#undef lenn_to_cpu
42ac26f2 RC	110
	111	#undef CONCAT_IMPL
	112	#undef CONCAT
	113	#undef CONCAT3