Merge tag 'v2021.10-rc4' into next

[thirdparty/u-boot.git] / arch / riscv / Kconfig

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 519507d57018919b043bd0b9caf575691d8d0074..ba29e70acf72979d4f89800d5183f14fcc62f437 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+       bool
+       help
+         This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
        bool
        depends on RISCV_MMODE || SPL_RISCV_MMODE