]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
usb: dwc3: add dis_u2_freeclk_exists_quirk
authorFrank Wang <frank.wang@rock-chips.com>
Tue, 26 May 2020 03:33:47 +0000 (11:33 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Fri, 29 May 2020 10:13:19 +0000 (18:13 +0800)
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h
include/dwc3-uboot.h

index 8b75de02aa8572895679ca485a821f5a0b4ff62e..83a0782adce478f2390d1f9a999737aa6140b65c 100644 (file)
@@ -403,6 +403,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
        if (dwc->dis_enblslpm_quirk)
                reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+       if (dwc->dis_u2_freeclk_exists_quirk)
+               reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
        mdelay(100);
@@ -725,6 +728,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
        dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
        dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
        dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
+       dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 
        dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
        if (dwc3_dev->tx_de_emphasis)
@@ -934,6 +938,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
                                "snps,dis-del-phy-power-chg-quirk");
        dwc->dis_enblslpm_quirk = dev_read_bool(dev,
                                "snps,dis_enblslpm_quirk");
+       dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
+                               "snps,dis-u2-freeclk-exists-quirk");
        dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
                                "snps,tx_de_emphasis_quirk");
        tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
index 91d028b4861cd293730ca70349534bb1810f4c04..b00e48585526e021a145aed6bdc0e1a519aa0f93 100644 (file)
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST    (1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS     (1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY                (1 << 6)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM      (1 << 8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)      ((n) << 3)
@@ -825,6 +826,7 @@ struct dwc3 {
        unsigned                dis_u2_susphy_quirk:1;
        unsigned                dis_del_phy_power_chg_quirk:1;
        unsigned                dis_enblslpm_quirk:1;
+       unsigned                dis_u2_freeclk_exists_quirk:1;
 
        unsigned                tx_de_emphasis_quirk:1;
        unsigned                tx_de_emphasis:2;
index 98d51e05e19e1b33bfd30e97918ea495e4fd688c..193d225d31a6ef226c4ad381d6f157fcc23d74c5 100644 (file)
@@ -35,6 +35,7 @@ struct dwc3_device {
        unsigned dis_u2_susphy_quirk;
        unsigned dis_del_phy_power_chg_quirk;
        unsigned dis_enblslpm_quirk;
+       unsigned dis_u2_freeclk_exists_quirk;
        unsigned tx_de_emphasis_quirk;
        unsigned tx_de_emphasis;
        int index;