]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
drivers: net: mc: Report extra memory to Linux
authorMeenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Thu, 23 May 2019 09:43:43 +0000 (15:13 +0530)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Thu, 22 Aug 2019 03:37:35 +0000 (09:07 +0530)
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
board/freescale/ls1088a/ls1088a.c
board/freescale/ls2080ardb/ls2080ardb.c
board/freescale/lx2160a/lx2160a.c
drivers/net/fsl-mc/mc.c
include/fsl-mc/fsl_mc.h

index f0bea7327db3a817c53e8048fe83c57d1b44eccb..690adc4c77e38b5293ed0dffa73cc4383260ca43 100644 (file)
@@ -739,11 +739,26 @@ void fsl_fdt_fixup_flash(void *fdt)
 int ft_board_setup(void *blob, bd_t *bd)
 {
        int i;
-       u64 base[CONFIG_NR_DRAM_BANKS];
-       u64 size[CONFIG_NR_DRAM_BANKS];
+       u16 mc_memory_bank = 0;
+
+       u64 *base;
+       u64 *size;
+       u64 mc_memory_base = 0;
+       u64 mc_memory_size = 0;
+       u16 total_memory_banks;
 
        ft_cpu_setup(blob, bd);
 
+       fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+       if (mc_memory_base != 0)
+               mc_memory_bank++;
+
+       total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+       base = calloc(total_memory_banks, sizeof(u64));
+       size = calloc(total_memory_banks, sizeof(u64));
+
        /* fixup DT for the two GPP DDR banks */
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
                base[i] = gd->bd->bi_dram[i].start;
@@ -760,7 +775,17 @@ int ft_board_setup(void *blob, bd_t *bd)
                size[1] = gd->arch.resv_ram - base[1];
 #endif
 
-       fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+       if (mc_memory_base != 0) {
+               for (i = 0; i <= total_memory_banks; i++) {
+                       if (base[i] == 0 && size[i] == 0) {
+                               base[i] = mc_memory_base;
+                               size[i] = mc_memory_size;
+                               break;
+                       }
+               }
+       }
+
+       fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 
        fdt_fsl_mc_fixup_iommu_map_entry(blob);
 
index 2b2dbbb0ce5486027794246f4bae26d15520036b..e000b1fd51174403535be2edb25c608c4139e3f6 100644 (file)
@@ -410,11 +410,27 @@ void fsl_fdt_fixup_flash(void *fdt)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-       u64 base[CONFIG_NR_DRAM_BANKS];
-       u64 size[CONFIG_NR_DRAM_BANKS];
+       int i;
+       u16 mc_memory_bank = 0;
+
+       u64 *base;
+       u64 *size;
+       u64 mc_memory_base = 0;
+       u64 mc_memory_size = 0;
+       u16 total_memory_banks;
 
        ft_cpu_setup(blob, bd);
 
+       fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+       if (mc_memory_base != 0)
+               mc_memory_bank++;
+
+       total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+       base = calloc(total_memory_banks, sizeof(u64));
+       size = calloc(total_memory_banks, sizeof(u64));
+
        /* fixup DT for the two GPP DDR banks */
        base[0] = gd->bd->bi_dram[0].start;
        size[0] = gd->bd->bi_dram[0].size;
@@ -431,7 +447,17 @@ int ft_board_setup(void *blob, bd_t *bd)
                size[1] = gd->arch.resv_ram - base[1];
 #endif
 
-       fdt_fixup_memory_banks(blob, base, size, 2);
+       if (mc_memory_base != 0) {
+               for (i = 0; i <= total_memory_banks; i++) {
+                       if (base[i] == 0 && size[i] == 0) {
+                               base[i] = mc_memory_base;
+                               size[i] = mc_memory_size;
+                               break;
+                       }
+               }
+       }
+
+       fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 
        fdt_fsl_mc_fixup_iommu_map_entry(blob);
 
index f3885fa8b7f84ebe76920f87db6af7d4b06da853..3dfbfebedc053f02d8267dd1f81954f8ded2591d 100644 (file)
@@ -529,11 +529,26 @@ void board_quiesce_devices(void)
 int ft_board_setup(void *blob, bd_t *bd)
 {
        int i;
-       u64 base[CONFIG_NR_DRAM_BANKS];
-       u64 size[CONFIG_NR_DRAM_BANKS];
+       u16 mc_memory_bank = 0;
+
+       u64 *base;
+       u64 *size;
+       u64 mc_memory_base = 0;
+       u64 mc_memory_size = 0;
+       u16 total_memory_banks;
 
        ft_cpu_setup(blob, bd);
 
+       fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+       if (mc_memory_base != 0)
+               mc_memory_bank++;
+
+       total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+       base = calloc(total_memory_banks, sizeof(u64));
+       size = calloc(total_memory_banks, sizeof(u64));
+
        /* fixup DT for the three GPP DDR banks */
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
                base[i] = gd->bd->bi_dram[i].start;
@@ -553,7 +568,17 @@ int ft_board_setup(void *blob, bd_t *bd)
                size[2] = gd->arch.resv_ram - base[2];
 #endif
 
-       fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+       if (mc_memory_base != 0) {
+               for (i = 0; i <= total_memory_banks; i++) {
+                       if (base[i] == 0 && size[i] == 0) {
+                               base[i] = mc_memory_base;
+                               size[i] = mc_memory_size;
+                               break;
+                       }
+               }
+       }
+
+       fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 
 #ifdef CONFIG_USB
        fsl_fdt_fixup_dr_usb(blob, bd);
index 1d96e4bdc2f112c1e47a361925f9401291ad3660..c980ba4edb9866c4b94c1ba0958a5a00f05aafdc 100644 (file)
@@ -282,6 +282,16 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
                                 MC_FIXUP_DPL);
 }
 
+void fdt_fixup_mc_ddr(u64 *base, u64 *size)
+{
+       u64 mc_size = mc_get_dram_block_size();
+
+       if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+               *base = mc_get_dram_addr() + mc_size;
+               *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+       }
+}
+
 void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
 {
        u32 *prop;
index 0abd797cc4609ff32a3d38ff95a7597c060fa2f0..a4d7d85fce7d64c85365ed2bdeeb574d8894f934 100644 (file)
@@ -55,6 +55,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
 int get_mc_boot_status(void);
 int get_dpl_apply_status(void);
 int is_lazy_dpl_addr_valid(void);
+void fdt_fixup_mc_ddr(u64 *base, u64 *size);
 #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
 int get_aiop_apply_status(void);
 #endif