Neil Armstrong [Wed, 20 Mar 2024 08:46:11 +0000 (09:46 +0100)]
board: amlogic: fix buffler overflow in seria, mac & usid read
While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set*() will buffer overflow and add random
characters to environment.
Christian Hewitt [Sun, 24 Mar 2024 15:19:05 +0000 (15:19 +0000)]
board: amlogic: add meson_generate_serial_ethaddr fallback to p200
Add a fall-back method to generate ethaddr from CPU serial on p200 boards
if the MAC cannot be read from efuse. This prevents random MAC addresses
on the WeTek Hub/Play2 boards.
Christian Hewitt [Sun, 24 Mar 2024 15:19:04 +0000 (15:19 +0000)]
ARM: dts: fix Ethernet on WeTek Hub/Play2
Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.
Increase the SPL_STACK_R_MALLOC_SIMPLE_LEN to 0x200000 to accommodate the
size of tispl.bin fit image. With the recent upgrade of ti-linux-firmware
from version v9.1.0 to v9.2.5, the size of tispl.bin fit image has
increased to 1.4MB, causing allocation errors in the R5 SPL:
```
alloc space exhausted
Could not get FIT buffer of 1325056 bytes
check CONFIG_SPL_SYS_MALLOC_SIZE
```
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Cc: kojima.masahisa@socionext.com Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Masahisa Kojima <kojima.masahisa@socionext.com>
arm: dts: k3-am625-verdin-r5: Change CPU frequency to 800MHz
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz") Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Douglas Anderson [Mon, 11 Mar 2024 21:02:45 +0000 (14:02 -0700)]
patman: Properly document the patchwork_url setting
The "Series-patchwork-url:" tag description says that it overrides the
settings file but doesn't specify the name of the setting. Elsewhere
in the documentation about the "useful" settings we see a setting that
sounds promising called "patchwork_server" that's actually not a valid
setting. It should be "patchwork_url".
Fix these problems so the doc is right and more useful.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
If bootefi selftest is executed and a problem with the device-tree
installation occurs, efi_install_fdt() writes sensible error messages.
It never returns EFI_INVALID_PARAMETER. It neither makes sense to check
for EFI_INVALID_PARAMETER nor to show the usage help for the bootefi
command in this case.
Hiago De Franco [Fri, 15 Mar 2024 21:56:57 +0000 (18:56 -0300)]
doc: board: apalis-imx8: Update and improve documentation
Update and improve the building documentation of Apalis iMX8.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Hiago De Franco [Fri, 15 Mar 2024 21:56:56 +0000 (18:56 -0300)]
doc: board: colibri-imx8x: Update and improve documentation
Update and improve the building documentation of Colibri iMX8X.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
- Fix build error when SoM detection on Phytec board.
- Fix sc_misc_otp_fuse_read() error check on colibri-imx8x/apalis-imx8.
- Fix NPU/VPU fdt disable fixup on i.MX8M.
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.
This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.
Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Commit bfb3409d676f ("imx: toradex/apalis-imx8: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():
- if (scierr == SC_ERR_NONE) {
+ if (scierr) {
/* QP has one A72 core disabled */
is_quadplus = ((val >> 4) & 0x3) != 0x0;
}
The other changes in this commit are correct.
sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
This inversion causes board_mem_get_layout() to report incorrect RAM size.
Go back the original error check logic to fix the problem.
Fixes: bfb3409d676f ("imx: toradex/apalis-imx8: correct SCU API usage") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Commit aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():
- if (sc_err == SC_ERR_NONE) {
+ if (sc_err) {
/* DX has two A35 cores disabled */
return (val & 0xf) != 0x0;
}
The other changes in this commit are correct.
sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
This inversion causes board_mem_get_layout() to report incorrect RAM size.
Go back the original error check logic to fix the problem.
Fixes: aa6e698a7acd ("imx: toradex/colibri-imx8x: correct SCU API usage") Reported-by: Hiago De Franco <hiago.franco@toradex.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X 1GB
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.
Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.
Benjamin Gray [Tue, 5 Mar 2024 18:52:03 +0000 (19:52 +0100)]
doc/sphinx: fix Python string escapes
Python 3.6 introduced a DeprecationWarning for invalid escape sequences.
This is upgraded to a SyntaxWarning in Python 3.12, and will eventually
be a syntax error.
Fix these now to get ahead of it before it's an error.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Message-ID: <20230912060801.95533-3-bgray@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Adapted for U-Boot Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Mark Kettenis [Thu, 15 Feb 2024 23:25:34 +0000 (00:25 +0100)]
efi_loader: Don't carve out memory reservations too early
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d
("efi_loader: create memory reservations in ACPI case")
broke boards that create additional memory reservations in
ft_board_setup() since it is now called before those additional
memory reservations are made. This is the case for the rk3588
boards and breaks booting OpenBSD on those boards.
Move the call back to its original location and add a call in
the code path used for ACPI.
Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI case") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Bo Gan [Wed, 6 Mar 2024 03:00:11 +0000 (19:00 -0800)]
riscv: dts: jh7110: Enable PLL node in SPL
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.
Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Conor Dooley [Mon, 4 Mar 2024 23:28:35 +0000 (23:28 +0000)]
riscv: cpu: improve multi-letter extension detection in supports_extension()
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x & z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x & z to prevent
this overrun, ignoring h.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
the .bss section. reserve_fdt() is called in board_init_f() to relocate the
device-tree to a safe location.
Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
the .bss section the device-tree is corrupted when _debug_uart_init() is
called in the SBI serial driver. Move the variable to the .data section.
Thomas Perrot [Thu, 22 Feb 2024 14:52:03 +0000 (15:52 +0100)]
riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s
It appears that there is some timing marginality either in the
board layout or the SoC that results in occasional data corruption
on some boards.
We observed this issue on some of the new HiFive Unmatched RevB
boards during volume production as well as some of the original
HiFive Unmatched boards from 2021 in our possession. This means
that there are other boards out there that might have the issue
too.
We have done some limited testing with DDR4 at 1600MT/s and
faulty boards (failing at 1866MT/s) passed.
We plan further testing after we procure a temperature chamber.
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tom Rini [Mon, 11 Mar 2024 13:22:44 +0000 (09:22 -0400)]
Merge tag 'u-boot-imx-master-20240311' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Use TF-A on imx8mp_beacon to fix boot regression.
- Use latest 6.8 dts for imx8mp_beacon.
- Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1.
- Describe the 0087 i.mx8m mini product variant in tdx-cfg-block.
Adam Ford [Sun, 10 Mar 2024 16:59:01 +0000 (11:59 -0500)]
arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8
The device tree has evolved over time, so re-sync. This also
partial reverts one change on the PCIe, because U-Boot doesn't
have a proper driver. However, since the clock is configured
to generate a 100MHz reference clock by default, a proper driver
isn't really necessary.
Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Thu, 7 Mar 2024 11:58:58 +0000 (05:58 -0600)]
configs: imx8mp_beacon: Fall back to using TF-A
When the board was originally added, it enabled some features which
allowed it to bypass Trusted Firmware, but as the feature set of
Linux grew and more features became available, the U-Boot config
options which bypassed TF-A caused issues, so it needs to return
to the standard operating mode of using TF-A or the system no
longer boots.
Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Benjamin Hahn [Wed, 6 Mar 2024 16:18:32 +0000 (17:18 +0100)]
board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1
We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.
Marek Vasut [Sun, 28 Jan 2024 01:19:40 +0000 (02:19 +0100)]
net: phy: Use PHY MDIO address from DT if available
In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tom Rini [Tue, 5 Mar 2024 12:08:10 +0000 (07:08 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
One fix makes the reboot more robust on some older board, another one
stabilises the initial clock setup on the A10/A20.
Two patches make sure our DRAM init does not actually change the content
of the DRAM array, which allows to use DRAM for Linux' pstore
functionality.
We get SPI support for U-Boot proper for one more SoC, that patch was
lingering around for a while, and should not affect other SoCs, so I am
merging this now.
As an added bonus, we get the defconfig file for a new board, the DT was
already synced from the kernel tree.
The CI looked happy with changes, and I tested them on five different
boards with different SoCs.
Josua Mayer [Fri, 2 Feb 2024 15:13:32 +0000 (16:13 +0100)]
arm: dts: armada-38x-solidrun-microsom: configure i2c0 bus
SolidRun Armada-388 SoM has an i2c bus supporting on-som eeprom, and
peripherals on a carrier.
armada-38x.dtsi disables this bus by default, it should be enabled by
som or carrier dts.
Linux has moved i2c0 from helios-4 board dts to som dtsi, including
status, pinctrl and clock speed.
Copy these settings from mainline.
This fixes accessing i2c bus from u-boot commandline.
The mv88e6xxx driver does not currently initialize the smi_addr field, but
instead keeps the default zero value. This leads to driver being unusable
on devices where the switch is not on address zero of the mdio bus. Fix
this problem by reading the SMI address from device tree.
Signed-off-by: Marek Mojík <marek.mojik@nic.cz> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Andrey Skvortsov [Wed, 27 Dec 2023 21:28:43 +0000 (00:28 +0300)]
sunxi: restore modified memory
Current sunxi DRAM initialisation code does several test accesses to the
DRAM array to detect aliasing effects and so determine the correct
row/column configuration. This changes the DRAM content, which breaks
use cases like soft reset and Linux's ramoops mechanism.
Fix this problem by saving and restoring the content of the DRAM cells
that is used for the test writes.
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andrey Skvortsov [Wed, 27 Dec 2023 21:28:42 +0000 (00:28 +0300)]
sunxi: reorganize mctl_mem_matches_* functions
mctl_mem_matches and mctl_mem_matches_base identical functions. To
avoid code duplication move them to dram_helpers and make
mctl_mem_matches use generic mctl_mem_matches_base.
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Commit 5d7a95f49999 ("imx6ul/imx6ull: synchronise device trees with
linux") removed the display timings from the board device tree whereas
they are still needed by the mxsfb driver.
Add the timings back (the correct ones) in the
imx6ul-opos6uldev-u-boot.dtsi file and remove them from the
opos6uldev.env file.
Update the opos6uldev_defconfig file so that the LCD turns on at boot.
Fixes: 5d7a95f49999 ("imx6ul/imx6ull: synchronise device trees with linux") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Andre Przywara [Tue, 30 Jan 2024 14:16:42 +0000 (14:16 +0000)]
sunxi: H616: Add OrangePi Zero 2W board support
The OrangePi Zero 2W is a tiny development board featuring the Allwinner
H618 SoC, shipping with up to 4GB of LPDDR4 DRAM, a mini-HDMI connector,
two USB Type-C sockets and a 16MB SPI NOR flash.
There is an FPC connector to connect an expansion board, which sports
two more USB Type-A sockets and a 100MBit Ethernet port. Support for
the expansion board is not in the DT yet, probably a DT overlay would
cover this in the future.
Add a defconfig file selecting the right drivers and DRAM options.
Since the .dts file was synced from the Linux kernel repo already, we
just need to add one line to the Makefile to actually build the .dtb.
The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Ludwig Kormann [Thu, 1 Feb 2024 08:45:50 +0000 (09:45 +0100)]
sunxi: sun4i: add missing sdelay() to clock_init_safe()
This delay is required after switching the clock source.
See “A20 Reference manual v1.4” Page 50 / section
“1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock
source is changed, at most to wait for 8 present running
clock cycles.”
This is already implemented in clock_set_pll1(), but was
still missing in clock_init_safe().
Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Philippe Coval [Sun, 11 Feb 2024 20:52:13 +0000 (21:52 +0100)]
arm: sunxi: Reduce inrush current on Olimex A20-OLinuXino_MICRO configs
This change fix reboot, both configurations
were tested on my Olimex A20 Micro Rev E with debian-12.
This issue was also present and fixed on A20 Lime2 (in 8311e84b18),
quoting Olliver Schinagl:
The lime2 features a too large capacitor on the LDO3 output, which
causes the PMIC to shutdown when enabling power. To be able to still
boot up however, we must gradually enable power on LDO3 for this board.
We do this by enabling both the inrush quirk and the maximum slope the
AXP209 supports.
Link: https://bugs.debian.org/1060752 Cc: Olliver Schinagl <oliver@schinagl.nl> Cc: Priit Laes <plaes@plaes.org> Cc: Maxime Ripard <mripard@kernel.org> Signed-off-by: Philippe Coval <rzr@users.sf.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Maksim Kiselev [Sat, 11 Nov 2023 13:33:08 +0000 (16:33 +0300)]
spi: sunxi: Add support for R329/D1/R528/T113 SPI controller
These SoCs have two SPI controllers that are quite similar to the SPI
on previous Allwinner SoCs. The main difference is that new SoCs
don't have a clock divider (SPI_CCR register) inside SPI IP.
Instead SPI sample mode should be configured depending on the input clock.
For now SPI input clock source selection is not supported by this driver,
and only HOSC@24MHz can be used as input clock. Therefore, according to
the, manual we could change the SPI sample mode from delay half
cycle(default) to normal.
This patch adds a quirk for this kind of SPI controllers
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:56 +0000 (17:05 +0100)]
ARM: renesas: Rename arch-/mach-rmobile to arch-/mach-renesas
Rename arch-rmobile to arch-renesas and mach-rmobile to mach-renesas
because all the chips are made by Renesas, while only a subset of
them is from the R-Mobile line.
Use the following command to perform the rename, with manual move of
the directories using git mv and manual fix up to arch/arm/Makefile:
Marek Vasut [Tue, 27 Feb 2024 16:05:53 +0000 (17:05 +0100)]
ARM: renesas: Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to CONFIG_RENESAS_EXTRAM_BOOT
Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to CONFIG_RMOBILE_EXTRAM_BOOT
because the former symbol does not exist and it is only incorrectly
converted CONFIG_RMOBILE_EXTRAM_BOOT which does exist. Replace the
RMOBILE with RENESAS because all the chips are made by Renesas, while
only a subset of them is from the R-Mobile line.
Use the following command to perform the rename with manual Kconfig.32 fix:
"
$ sed -i 's@CONFIG_ARCH_RMOBILE_EXTRAM_BOOT@CONFIG_RMOBILE_EXTRAM_BOOT@g' board/renesas/*/*
$ sed -i 's@CONFIG_RMOBILE_EXTRAM_BOOT@CONFIG_RENESAS_EXTRAM_BOOT@g' board/renesas/*/*
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:52 +0000 (17:05 +0100)]
ARM: renesas: Rename ARCH_RMOBILE_BOARD_STRING to ARCH_RENESAS_BOARD_STRING
Rename ARCH_RMOBILE_BOARD_STRING to ARCH_RENESAS_BOARD_STRING
because all the chips are made by Renesas, while only a subset
of them is from the R-Mobile line.
Marek Vasut [Tue, 27 Feb 2024 16:05:50 +0000 (17:05 +0100)]
ARM: renesas: Simplify weak symbols
Simplify the weak symbols use in cpu_info.c by using the __weak macro.
The result is identical, but the syntax is much simpler. Furthermore,
drop three more rmobile* symbols which are now unused.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:48 +0000 (17:05 +0100)]
ARM: renesas: Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx()
Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx() because all
the chips are made by Renesas, while only a subset of them is from
the R-Mobile line.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:46 +0000 (17:05 +0100)]
ARM: renesas: Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*()
Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because
all the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.
Marek Vasut [Tue, 27 Feb 2024 16:05:45 +0000 (17:05 +0100)]
ARM: renesas: Rename rmobile_get_cpu_type() to renesas_get_cpu_type()
Rename rmobile_get_cpu_type() to renesas_get_cpu_type() because
all the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.
Marek Vasut [Tue, 27 Feb 2024 16:05:44 +0000 (17:05 +0100)]
ARM: renesas: Drop unused pfc-r8a7790.h
This file is no longer used, the PFC pin controller driver is
superseded by drivers/pinctrl/renesas/pfc-r8a7790.c which
includes all the details of the hardware. Remove this file.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:43 +0000 (17:05 +0100)]
ARM: renesas: Drop unused mmc.h
This file is no longer used, the MMCIF controller driver is
superseded by drivers/mmc/sh_mmcif.c which includes all the
details of the hardware. Remove this file include from all
board files and remove the file itself. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Marek Vasut [Tue, 27 Feb 2024 16:05:42 +0000 (17:05 +0100)]
ARM: renesas: Drop unused sh_sdhi.h
This file is no longer used, the SDHI controller driver is long
superseded by drivers/mmc/renesas-sdhi.c which includes all the
details of the hardware. Remove this file include from all board
files and remove the file itself. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Aradhya Bhatia [Mon, 12 Feb 2024 10:06:35 +0000 (15:36 +0530)]
arm: mach-k3: Refactor QoS settings
Refactor common QoS code into a new common header file, and the soc
specific setup_qos functions into a common API.
Rename $(soc)_qos_count and $(soc)_qos_data variables to qos_count and
qos_data. When QoS settings of more SoCs are added, only one pair will
be defined at a time, based on the config SOC_K3_$(soc).
This refactoring has been done for 2 major purposes.
- The auto-generated $(soc)_qos_data.c and $(soc)_qos.h files cannot
have any code that is specific to any bootloader. Those files have to
remain agnostic of different bootloader implementations and their
header files.
- The existing implementation was less than ideal and would have enabled
multiple $(soc)_qos_count and $(soc)_qos_data variables for all SoC
variants.
projects / thirdparty / u-boot.git / log
