[u-boot.git] / arch / powerpc / cpu / ppc4xx / ecc.h

/*
 *    Copyright (c) 2008 Nuovation System Designs, LLC
 *	Grant Erickson <gerickson@nuovations.com>
 *
 *    Copyright (c) 2007-2009 DENX Software Engineering, GmbH
 *	Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 *    Description:
 *	This file implements ECC initialization for PowerPC processors
 *	using the IBM SDRAM DDR1 & DDR2 controller.
 */

#ifndef _ECC_H_
#define _ECC_H_

/*
 * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
 * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
 * we need to make some processor dependant defines used later on by the
 * driver.
 */

/* For 440GP/GX/EP/GR */
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
#define SDRAM_MCOPT1		SDRAM_CFG0
#define SDRAM_MCOPT1_MCHK_MASK	SDRAM_CFG0_MCHK_MASK
#define SDRAM_MCOPT1_MCHK_NON	SDRAM_CFG0_MCHK_NON
#define SDRAM_MCOPT1_MCHK_GEN	SDRAM_CFG0_MCHK_GEN
#define SDRAM_MCOPT1_MCHK_CHK	SDRAM_CFG0_MCHK_CHK
#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
#define SDRAM_MCOPT1_DMWD_MASK	SDRAM_CFG0_DMWD_MASK
#define SDRAM_MCOPT1_DMWD_32	SDRAM_CFG0_DMWD_32

#define SDRAM_MCSTAT		SDRAM0_MCSTS
#define SDRAM_MCSTAT_IDLE_MASK	SDRAM_MCSTS_CIS
#define SDRAM_MCSTAT_IDLE_NOT	SDRAM_MCSTS_IDLE_NOT

#define SDRAM_ECCES		SDRAM0_ECCESR
#endif

void ecc_init(unsigned long * const start, unsigned long size);
void do_program_ecc(unsigned long tlb_word2_i_value);

static void inline blank_string(int size)
{
	int i;

	for (i = 0; i < size; i++)
		putc('\b');
	for (i = 0; i < size; i++)
		putc(' ');
	for (i = 0; i < size; i++)
		putc('\b');
}

#endif /* _ECC_H_ */
Commit	Line	Data
c821b5f1 GE	1	/*
	2	* Copyright (c) 2008 Nuovation System Designs, LLC
	3	* Grant Erickson <gerickson@nuovations.com>
	4	*
fb95169e	5	* Copyright (c) 2007-2009 DENX Software Engineering, GmbH
c821b5f1 GE	6	* Stefan Roese <sr@denx.de>
c821b5f1 GE	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c821b5f1 GE	9	*
	10	* Description:
	11	* This file implements ECC initialization for PowerPC processors
fb95169e	12	* using the IBM SDRAM DDR1 & DDR2 controller.
c821b5f1 GE	13	*/
	14
	15	#ifndef _ECC_H_
	16	#define _ECC_H_
	17
39b32be1 SR	18	/*
	19	* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
	20	* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
	21	* we need to make some processor dependant defines used later on by the
	22	* driver.
	23	*/
	24
	25	/* For 440GP/GX/EP/GR */
	26	#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
fb95169e SR	27	#define SDRAM_MCOPT1 SDRAM_CFG0
	28	#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
	29	#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON
	30	#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN
	31	#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK
	32	#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
	33	#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
	34	#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32
	35
	36	#define SDRAM_MCSTAT SDRAM0_MCSTS
	37	#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
	38	#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT
39b32be1	39
fb95169e	40	#define SDRAM_ECCES SDRAM0_ECCESR
39b32be1 SR	41	#endif
39b32be1 SR	42
fb95169e SR	43	void ecc_init(unsigned long * const start, unsigned long size);
	44	void do_program_ecc(unsigned long tlb_word2_i_value);
	45
	46	static void inline blank_string(int size)
	47	{
	48	int i;
	49
	50	for (i = 0; i < size; i++)
	51	putc('\b');
	52	for (i = 0; i < size; i++)
	53	putc(' ');
	54	for (i = 0; i < size; i++)
	55	putc('\b');
	56	}
c821b5f1 GE	57
c821b5f1 GE	58	#endif /* _ECC_H_ */