[u-boot.git] / arch / powerpc / cpu / ppc4xx / sdram.c

/*
 * (C) Copyright 2005-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2006
 * DAVE Srl <www.dave-tech.it>
 *
 * (C) Copyright 2002-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#include "sdram.h"
#include "ecc.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SDRAM_BANK0

#ifndef CONFIG_440

#ifndef CONFIG_SYS_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
	{(128 << 20), 13, 0x000A4001},	    /* (0-128MB) Address Mode 3, 13x10(4) */
	{(64 << 20),  13, 0x00084001},	    /* (0-64MB) Address Mode 3, 13x9(4)	  */
	{(32 << 20),  12, 0x00062001},	    /* (0-32MB) Address Mode 2, 12x9(4)	  */
	{(16 << 20),  12, 0x00046001},	    /* (0-16MB) Address Mode 4, 12x8(4)	  */
	{(4 << 20),   11, 0x00008001},	    /* (0-4MB) Address Mode 5, 11x8(2)	  */
};
#else
sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif

#define N_MB0CF (ARRAY_SIZE(mb0cf))

#ifdef CONFIG_SYS_SDRAM_CASL
static ulong ns2clks(ulong ns)
{
	ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);

	return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
}
#endif /* CONFIG_SYS_SDRAM_CASL */

static ulong compute_sdtr1(ulong speed)
{
#ifdef CONFIG_SYS_SDRAM_CASL
	ulong tmp;
	ulong sdtr1 = 0;

	/* CASL */
	if (CONFIG_SYS_SDRAM_CASL < 2)
		sdtr1 |= (1 << SDRAM0_TR_CASL);
	else
		if (CONFIG_SYS_SDRAM_CASL > 4)
			sdtr1 |= (3 << SDRAM0_TR_CASL);
		else
			sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);

	/* PTA */
	tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
	if ((tmp >= 2) && (tmp <= 4))
		sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
	else
		sdtr1 |= ((4-1) << SDRAM0_TR_PTA);

	/* CTP */
	tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
	if ((tmp >= 2) && (tmp <= 4))
		sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
	else
		sdtr1 |= ((4-1) << SDRAM0_TR_CTP);

	/* LDF */
	tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
	if ((tmp >= 2) && (tmp <= 4))
		sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
	else
		sdtr1 |= ((2-1) << SDRAM0_TR_LDF);

	/* RFTA */
	tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
	if ((tmp >= 4) && (tmp <= 10))
		sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
	else
		sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);

	/* RCD */
	tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
	if ((tmp >= 2) && (tmp <= 4))
		sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
	else
		sdtr1 |= ((4-1) << SDRAM0_TR_RCD);

	return sdtr1;
#else /* CONFIG_SYS_SDRAM_CASL */
	/*
	 * If no values are configured in the board config file
	 * use the default values, which seem to be ok for most
	 * boards.
	 *
	 * REMARK:
	 * For new board ports we strongly recommend to define the
	 * correct values for the used SDRAM chips in your board
	 * config file (see PPChameleonEVB.h)
	 */
	if (speed > 100000000) {
		/*
		 * 133 MHz SDRAM
		 */
		return 0x01074015;
	} else {
		/*
		 * default: 100 MHz SDRAM
		 */
		return 0x0086400d;
	}
#endif /* CONFIG_SYS_SDRAM_CASL */
}

/* refresh is expressed in ms */
static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
{
#ifdef CONFIG_SYS_SDRAM_CASL
	ulong tmp;

	tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
	tmp /= 1000000;

	return ((tmp & 0x00003FF8) << 16);
#else /* CONFIG_SYS_SDRAM_CASL */
	if (speed > 100000000) {
		/*
		 * 133 MHz SDRAM
		 */
		return 0x07f00000;
	} else {
		/*
		 * default: 100 MHz SDRAM
		 */
		return 0x05f00000;
	}
#endif /* CONFIG_SYS_SDRAM_CASL */
}

/*
 * Autodetect onboard SDRAM on 405 platforms
 */
int dram_init(void)
{
	ulong speed;
	ulong sdtr1;
	int i;

	/*
	 * Determine SDRAM speed
	 */
	speed = get_bus_freq(0); /* parameter not used on ppc4xx */

	/*
	 * sdtr1 (register SDRAM0_TR) must take into account timings listed
	 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
	 * account actual SDRAM size. So we can set up sdtr1 according to what
	 * is specified in board configuration file while rtr dependds on SDRAM
	 * size we are assuming before detection.
	 */
	sdtr1 = compute_sdtr1(speed);

	for (i=0; i<N_MB0CF; i++) {
		/*
		 * Disable memory controller.
		 */
		mtsdram(SDRAM0_CFG, 0x00000000);

		/*
		 * Set MB0CF for bank 0.
		 */
		mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
		mtsdram(SDRAM0_TR, sdtr1);
		mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));

		udelay(200);

		/*
		 * Set memory controller options reg, MCOPT1.
		 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
		 * read/prefetch.
		 */
		mtsdram(SDRAM0_CFG, 0x80800000);

		udelay(10000);

		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
			phys_size_t size = mb0cf[i].size;

			/*
			 * OK, size detected.  Enable second bank if
			 * defined (assumes same type as bank 0)
			 */
#ifdef CONFIG_SDRAM_BANK1
			mtsdram(SDRAM0_CFG, 0x00000000);
			mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
			mtsdram(SDRAM0_CFG, 0x80800000);
			udelay(10000);

			/*
			 * Check if 2nd bank is really available.
			 * If the size not equal to the size of the first
			 * bank, then disable the 2nd bank completely.
			 */
			if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
			    mb0cf[i].size) {
				mtsdram(SDRAM0_B1CR, 0);
				mtsdram(SDRAM0_CFG, 0);
			} else {
				/*
				 * We have two identical banks, so the size
				 * is twice the bank size
				 */
				size = 2 * size;
			}
#endif

			/*
			 * OK, size detected -> all done
			 */
			gd->ram_size = size;

			return 0;
		}
	}

	return -ENXIO;
}

#else /* CONFIG_440 */

/*
 * Define some default values. Those can be overwritten in the
 * board config file.
 */

#ifndef CONFIG_SYS_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
	{(256 << 20), 13, 0x000C4001},	/* 256MB mode 3, 13x10(4)	*/
	{(128 << 20), 13, 0x000A4001},	/* 128MB mode 3, 13x10(4)	*/
	{(64 << 20),  12, 0x00082001}	/* 64MB mode 2, 12x9(4)		*/
};
#else
sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
#endif

#ifndef CONFIG_SYS_SDRAM0_TR0
#define	CONFIG_SYS_SDRAM0_TR0		0x41094012
#endif

#ifndef CONFIG_SYS_SDRAM0_WDDCTR
#define CONFIG_SYS_SDRAM0_WDDCTR	0x00000000  /* wrcp=0 dcd=0	*/
#endif

#ifndef CONFIG_SYS_SDRAM0_RTR
#define CONFIG_SYS_SDRAM0_RTR 		0x04100000 /* 7.8us @ 133MHz PLB */
#endif

#ifndef CONFIG_SYS_SDRAM0_CFG0
#define CONFIG_SYS_SDRAM0_CFG0		0x82000000 /* DCEN=1, PMUD=0, 64-bit */
#endif

#define N_MB0CF (ARRAY_SIZE(mb0cf))

#define NUM_TRIES 64
#define NUM_READS 10

static void sdram_tr1_set(int ram_address, int* tr1_value)
{
	int i;
	int j, k;
	volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
	int first_good = -1, last_bad = 0x1ff;

	unsigned long test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	/* go through all possible SDRAM0_TR1[RDCT] values */
	for (i=0; i<=0x1ff; i++) {
		/* set the current value for TR1 */
		mtsdram(SDRAM0_TR1, (0x80800800 | i));

		/* write values */
		for (j=0; j<NUM_TRIES; j++) {
			ram_pointer[j] = test[j];

			/* clear any cache at ram location */
			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
		}

		/* read values back */
		for (j=0; j<NUM_TRIES; j++) {
			for (k=0; k<NUM_READS; k++) {
				/* clear any cache at ram location */
				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));

				if (ram_pointer[j] != test[j])
					break;
			}

			/* read error */
			if (k != NUM_READS)
				break;
		}

		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
		if (j == NUM_TRIES) {
			if (first_good == -1)
				first_good = i;		/* found beginning of window */
		} else { /* bad read */
			/* if we have not had a good read then don't care */
			if (first_good != -1) {
				/* first failure after a good read */
				last_bad = i-1;
				break;
			}
		}
	}

	/* return the current value for TR1 */
	*tr1_value = (first_good + last_bad) / 2;
}

/*
 * Autodetect onboard DDR SDRAM on 440 platforms
 *
 * NOTE: Some of the hardcoded values are hardware dependant,
 *	 so this should be extended for other future boards
 *	 using this routine!
 */
int dram_init(void)
{
	int i;
	int tr1_bank1;

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
    defined(CONFIG_440GR) || defined(CONFIG_440SP)
	/*
	 * Soft-reset SDRAM controller.
	 */
	mtsdr(SDR0_SRST, SDR0_SRST_DMC);
	mtsdr(SDR0_SRST, 0x00000000);
#endif

	for (i=0; i<N_MB0CF; i++) {
		/*
		 * Disable memory controller.
		 */
		mtsdram(SDRAM0_CFG0, 0x00000000);

		/*
		 * Setup some default
		 */
		mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default)		*/
		mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0		*/
		mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal)		*/
		mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
		mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0	*/

		/*
		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
		 */
		mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
		mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
		mtsdram(SDRAM0_TR1, 0x80800800);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
		mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
		mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM*/
		udelay(400);			/* Delay 200 usecs (min)	*/

		/*
		 * Enable the controller, then wait for DCEN to complete
		 */
		mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
		udelay(10000);

		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
			phys_size_t size = mb0cf[i].size;
			/*
			 * Optimize TR1 to current hardware environment
			 */
			sdram_tr1_set(0x00000000, &tr1_bank1);
			mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));


			/*
			 * OK, size detected.  Enable second bank if
			 * defined (assumes same type as bank 0)
			 */
#ifdef CONFIG_SDRAM_BANK1
			mtsdram(SDRAM0_CFG0, 0);
			mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
			mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
			udelay(10000);

			/*
			 * Check if 2nd bank is really available.
			 * If the size not equal to the size of the first
			 * bank, then disable the 2nd bank completely.
			 */
			if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
			    != mb0cf[i].size) {
				mtsdram(SDRAM0_CFG0, 0);
				mtsdram(SDRAM0_B1CR, 0);
				mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
				udelay(10000);
			} else {
				/*
				 * We have two identical banks, so the size
				 * is twice the bank size
				 */
				size = 2 * size;
			}
#endif

#ifdef CONFIG_SDRAM_ECC
			ecc_init(0, size);
#endif

			/*
			 * OK, size detected -> all done
			 */
			gd->ram_size = size;

			return 0;
		}
	}

	return -ENXIO;			/* nothing found !		*/
}

#endif /* CONFIG_440 */

#endif /* CONFIG_SDRAM_BANK0 */
Commit	Line	Data
c609719b	1	/*
5fb692ca	2	* (C) Copyright 2005-2007
5568e613 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
5568e613 SR	4	*
62534beb SR	5	* (C) Copyright 2006
	6	* DAVE Srl <www.dave-tech.it>
	7	*
de8d5a36	8	* (C) Copyright 2002-2004
c609719b WD	9	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
c609719b WD	10	*
3765b3e7	11	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	12	*/
	13
	14	#include <common.h>
b36df561	15	#include <asm/ppc4xx.h>
c609719b	16	#include <asm/processor.h>
62534beb	17	#include "sdram.h"
c821b5f1	18	#include "ecc.h"
c609719b	19
088454cd SG	20	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	21
c609719b WD	22	#ifdef CONFIG_SDRAM_BANK0
c609719b WD	23
5fb692ca	24	#ifndef CONFIG_440
c609719b	25
6d0f6bcf	26	#ifndef CONFIG_SYS_SDRAM_TABLE
de8d5a36	27	sdram_conf_t mb0cf[] = {
cf48eb9a WD	28	{(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
	29	{(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
	30	{(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
	31	{(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
	32	{(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
de8d5a36	33	};
5568e613	34	#else
6d0f6bcf	35	sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
5568e613 SR	36	#endif
5568e613 SR	37
b7707b04	38	#define N_MB0CF (ARRAY_SIZE(mb0cf))
c609719b	39
6d0f6bcf	40	#ifdef CONFIG_SYS_SDRAM_CASL
62534beb SR	41	static ulong ns2clks(ulong ns)
	42	{
	43	ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
	44
	45	return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
	46	}
6d0f6bcf	47	#endif /* CONFIG_SYS_SDRAM_CASL */
62534beb SR	48
	49	static ulong compute_sdtr1(ulong speed)
	50	{
6d0f6bcf	51	#ifdef CONFIG_SYS_SDRAM_CASL
cf48eb9a WD	52	ulong tmp;
	53	ulong sdtr1 = 0;
	54
	55	/* CASL */
6d0f6bcf	56	if (CONFIG_SYS_SDRAM_CASL < 2)
cf48eb9a WD	57	sdtr1 \|= (1 << SDRAM0_TR_CASL);
cf48eb9a WD	58	else
6d0f6bcf	59	if (CONFIG_SYS_SDRAM_CASL > 4)
cf48eb9a WD	60	sdtr1 \|= (3 << SDRAM0_TR_CASL);
cf48eb9a WD	61	else
6d0f6bcf	62	sdtr1 \|= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
cf48eb9a WD	63
cf48eb9a WD	64	/* PTA */
6d0f6bcf	65	tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
cf48eb9a WD	66	if ((tmp >= 2) && (tmp <= 4))
	67	sdtr1 \|= ((tmp-1) << SDRAM0_TR_PTA);
	68	else
	69	sdtr1 \|= ((4-1) << SDRAM0_TR_PTA);
	70
	71	/* CTP */
6d0f6bcf	72	tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
cf48eb9a WD	73	if ((tmp >= 2) && (tmp <= 4))
	74	sdtr1 \|= ((tmp-1) << SDRAM0_TR_CTP);
	75	else
	76	sdtr1 \|= ((4-1) << SDRAM0_TR_CTP);
	77
	78	/* LDF */
6d0f6bcf	79	tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
cf48eb9a WD	80	if ((tmp >= 2) && (tmp <= 4))
	81	sdtr1 \|= ((tmp-1) << SDRAM0_TR_LDF);
	82	else
	83	sdtr1 \|= ((2-1) << SDRAM0_TR_LDF);
	84
	85	/* RFTA */
6d0f6bcf	86	tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
cf48eb9a WD	87	if ((tmp >= 4) && (tmp <= 10))
	88	sdtr1 \|= ((tmp-4) << SDRAM0_TR_RFTA);
	89	else
	90	sdtr1 \|= ((10-4) << SDRAM0_TR_RFTA);
	91
	92	/* RCD */
6d0f6bcf	93	tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
cf48eb9a WD	94	if ((tmp >= 2) && (tmp <= 4))
	95	sdtr1 \|= ((tmp-1) << SDRAM0_TR_RCD);
	96	else
	97	sdtr1 \|= ((4-1) << SDRAM0_TR_RCD);
	98
	99	return sdtr1;
6d0f6bcf	100	#else /* CONFIG_SYS_SDRAM_CASL */
cf48eb9a WD	101	/*
	102	* If no values are configured in the board config file
	103	* use the default values, which seem to be ok for most
	104	* boards.
	105	*
	106	* REMARK:
	107	* For new board ports we strongly recommend to define the
	108	* correct values for the used SDRAM chips in your board
	109	* config file (see PPChameleonEVB.h)
	110	*/
	111	if (speed > 100000000) {
	112	/*
	113	* 133 MHz SDRAM
	114	*/
	115	return 0x01074015;
	116	} else {
	117	/*
	118	* default: 100 MHz SDRAM
	119	*/
	120	return 0x0086400d;
	121	}
6d0f6bcf	122	#endif /* CONFIG_SYS_SDRAM_CASL */
62534beb SR	123	}
	124
	125	/* refresh is expressed in ms */
	126	static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
	127	{
6d0f6bcf	128	#ifdef CONFIG_SYS_SDRAM_CASL
cf48eb9a	129	ulong tmp;
62534beb	130
cf48eb9a WD	131	tmp = ((refresh10001000) / (1 << rows)) * (speed / 1000);
cf48eb9a WD	132	tmp /= 1000000;
62534beb	133
cf48eb9a	134	return ((tmp & 0x00003FF8) << 16);
6d0f6bcf	135	#else /* CONFIG_SYS_SDRAM_CASL */
cf48eb9a WD	136	if (speed > 100000000) {
	137	/*
	138	* 133 MHz SDRAM
	139	*/
62534beb	140	return 0x07f00000;
cf48eb9a WD	141	} else {
	142	/*
	143	* default: 100 MHz SDRAM
	144	*/
62534beb	145	return 0x05f00000;
cf48eb9a	146	}
6d0f6bcf	147	#endif /* CONFIG_SYS_SDRAM_CASL */
62534beb SR	148	}
62534beb SR	149
5568e613 SR	150	/*
	151	* Autodetect onboard SDRAM on 405 platforms
	152	*/
f1683aa7	153	int dram_init(void)
c609719b	154	{
62534beb	155	ulong speed;
c609719b	156	ulong sdtr1;
de8d5a36	157	int i;
c609719b	158
cf48eb9a WD	159	/*
	160	* Determine SDRAM speed
	161	*/
	162	speed = get_bus_freq(0); /* parameter not used on ppc4xx */
62534beb	163
cf48eb9a WD	164	/*
	165	* sdtr1 (register SDRAM0_TR) must take into account timings listed
	166	* in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
	167	* account actual SDRAM size. So we can set up sdtr1 according to what
	168	* is specified in board configuration file while rtr dependds on SDRAM
	169	* size we are assuming before detection.
	170	*/
	171	sdtr1 = compute_sdtr1(speed);
c609719b	172
de8d5a36	173	for (i=0; i<N_MB0CF; i++) {
6177445d	174	/*
de8d5a36	175	* Disable memory controller.
6177445d	176	*/
95b602ba	177	mtsdram(SDRAM0_CFG, 0x00000000);
e5ad56b1	178
c609719b	179	/*
de8d5a36	180	* Set MB0CF for bank 0.
c609719b	181	*/
95b602ba SR	182	mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
	183	mtsdram(SDRAM0_TR, sdtr1);
	184	mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
e5ad56b1	185
de8d5a36	186	udelay(200);
c609719b	187
c609719b	188	/*
de8d5a36 SR	189	* Set memory controller options reg, MCOPT1.
	190	* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
	191	* read/prefetch.
c609719b	192	*/
95b602ba	193	mtsdram(SDRAM0_CFG, 0x80800000);
c609719b	194
de8d5a36	195	udelay(10000);
c609719b	196
de8d5a36	197	if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
7bf5ecfa SR	198	phys_size_t size = mb0cf[i].size;
7bf5ecfa SR	199
de8d5a36	200	/*
d4024bb7 JO	201	* OK, size detected. Enable second bank if
d4024bb7 JO	202	* defined (assumes same type as bank 0)
de8d5a36	203	*/
d4024bb7	204	#ifdef CONFIG_SDRAM_BANK1
95b602ba SR	205	mtsdram(SDRAM0_CFG, 0x00000000);
	206	mtsdram(SDRAM0_B1CR, mb0cf[i].size \| mb0cf[i].reg);
	207	mtsdram(SDRAM0_CFG, 0x80800000);
d4024bb7	208	udelay(10000);
779e9751 SR	209
	210	/*
	211	* Check if 2nd bank is really available.
	212	* If the size not equal to the size of the first
	213	* bank, then disable the 2nd bank completely.
	214	*/
	215	if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
	216	mb0cf[i].size) {
95b602ba SR	217	mtsdram(SDRAM0_B1CR, 0);
95b602ba SR	218	mtsdram(SDRAM0_CFG, 0);
7bf5ecfa SR	219	} else {
	220	/*
	221	* We have two identical banks, so the size
	222	* is twice the bank size
	223	*/
	224	size = 2 * size;
779e9751	225	}
d4024bb7	226	#endif
bbeff30c SR	227
	228	/*
	229	* OK, size detected -> all done
	230	*/
088454cd SG	231	gd->ram_size = size;
	232
	233	return 0;
de8d5a36	234	}
6177445d	235	}
bbeff30c	236
088454cd	237	return -ENXIO;
c609719b WD	238	}
c609719b WD	239
5568e613 SR	240	#else /* CONFIG_440 */
5568e613 SR	241
5fb692ca SR	242	/*
	243	* Define some default values. Those can be overwritten in the
	244	* board config file.
	245	*/
	246
6d0f6bcf	247	#ifndef CONFIG_SYS_SDRAM_TABLE
5fb692ca SR	248	sdram_conf_t mb0cf[] = {
5fb692ca SR	249	{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
3943d2ff	250	{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */
5fb692ca SR	251	{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
	252	};
	253	#else
6d0f6bcf	254	sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
5fb692ca SR	255	#endif
5fb692ca SR	256
6d0f6bcf JCPV	257	#ifndef CONFIG_SYS_SDRAM0_TR0
6d0f6bcf JCPV	258	#define CONFIG_SYS_SDRAM0_TR0 0x41094012
5fb692ca SR	259	#endif
5fb692ca SR	260
3943d2ff DE	261	#ifndef CONFIG_SYS_SDRAM0_WDDCTR
	262	#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */
	263	#endif
	264
	265	#ifndef CONFIG_SYS_SDRAM0_RTR
	266	#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */
	267	#endif
	268
	269	#ifndef CONFIG_SYS_SDRAM0_CFG0
	270	#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
	271	#endif
	272
b7707b04	273	#define N_MB0CF (ARRAY_SIZE(mb0cf))
5fb692ca	274
62534beb SR	275	#define NUM_TRIES 64
	276	#define NUM_READS 10
	277
	278	static void sdram_tr1_set(int ram_address, int* tr1_value)
	279	{
	280	int i;
	281	int j, k;
	282	volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
	283	int first_good = -1, last_bad = 0x1ff;
	284
	285	unsigned long test[NUM_TRIES] = {
	286	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	287	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	288	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	289	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	290	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	291	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	292	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	293	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	294	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	295	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	296	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	297	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	298	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	299	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	300	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
	301	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
	302
	303	/* go through all possible SDRAM0_TR1[RDCT] values */
	304	for (i=0; i<=0x1ff; i++) {
	305	/* set the current value for TR1 */
95b602ba	306	mtsdram(SDRAM0_TR1, (0x80800800 \| i));
62534beb SR	307
	308	/* write values */
	309	for (j=0; j<NUM_TRIES; j++) {
	310	ram_pointer[j] = test[j];
	311
	312	/* clear any cache at ram location */
	313	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	314	}
	315
	316	/* read values back */
	317	for (j=0; j<NUM_TRIES; j++) {
	318	for (k=0; k<NUM_READS; k++) {
	319	/* clear any cache at ram location */
	320	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	321
	322	if (ram_pointer[j] != test[j])
	323	break;
	324	}
	325
	326	/* read error */
	327	if (k != NUM_READS)
	328	break;
	329	}
	330
	331	/* we have a SDRAM0_TR1[RDCT] that is part of the window */
	332	if (j == NUM_TRIES) {
	333	if (first_good == -1)
	334	first_good = i; /* found beginning of window */
	335	} else { /* bad read */
	336	/* if we have not had a good read then don't care */
	337	if (first_good != -1) {
	338	/* first failure after a good read */
	339	last_bad = i-1;
	340	break;
	341	}
	342	}
	343	}
	344
	345	/* return the current value for TR1 */
	346	*tr1_value = (first_good + last_bad) / 2;
	347	}
	348
5568e613 SR	349	/*
	350	* Autodetect onboard DDR SDRAM on 440 platforms
	351	*
	352	* NOTE: Some of the hardcoded values are hardware dependant,
cf48eb9a WD	353	* so this should be extended for other future boards
cf48eb9a WD	354	* using this routine!
5568e613	355	*/
f1683aa7	356	int dram_init(void)
5568e613 SR	357	{
5568e613 SR	358	int i;
62534beb	359	int tr1_bank1;
5568e613	360
5fb692ca SR	361	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| \
5fb692ca SR	362	defined(CONFIG_440GR) \|\| defined(CONFIG_440SP)
899620c2 SR	363	/*
	364	* Soft-reset SDRAM controller.
	365	*/
d1c3b275 SR	366	mtsdr(SDR0_SRST, SDR0_SRST_DMC);
d1c3b275 SR	367	mtsdr(SDR0_SRST, 0x00000000);
899620c2 SR	368	#endif
899620c2 SR	369
5568e613 SR	370	for (i=0; i<N_MB0CF; i++) {
	371	/*
	372	* Disable memory controller.
	373	*/
95b602ba	374	mtsdram(SDRAM0_CFG0, 0x00000000);
5568e613 SR	375
	376	/*
	377	* Setup some default
	378	*/
95b602ba SR	379	mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
	380	mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	381	mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
	382	mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
	383	mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
5568e613 SR	384
	385	/*
	386	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	387	*/
95b602ba SR	388	mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
	389	mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
	390	mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
	391	mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
	392	mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
5568e613 SR	393	udelay(400); /* Delay 200 usecs (min) */
	394
	395	/*
	396	* Enable the controller, then wait for DCEN to complete
	397	*/
95b602ba	398	mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
5568e613 SR	399	udelay(10000);
	400
	401	if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
3943d2ff	402	phys_size_t size = mb0cf[i].size;
62534beb SR	403	/*
	404	* Optimize TR1 to current hardware environment
	405	*/
	406	sdram_tr1_set(0x00000000, &tr1_bank1);
95b602ba	407	mtsdram(SDRAM0_TR1, (tr1_bank1 \| 0x80800800));
62534beb	408
3943d2ff DE	409
	410	/*
	411	* OK, size detected. Enable second bank if
	412	* defined (assumes same type as bank 0)
	413	*/
	414	#ifdef CONFIG_SDRAM_BANK1
95b602ba SR	415	mtsdram(SDRAM0_CFG0, 0);
	416	mtsdram(SDRAM0_B1CR, mb0cf[i].size \| mb0cf[i].reg);
	417	mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
3943d2ff DE	418	udelay(10000);
	419
	420	/*
	421	* Check if 2nd bank is really available.
	422	* If the size not equal to the size of the first
	423	* bank, then disable the 2nd bank completely.
	424	*/
	425	if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
	426	!= mb0cf[i].size) {
95b602ba SR	427	mtsdram(SDRAM0_CFG0, 0);
	428	mtsdram(SDRAM0_B1CR, 0);
	429	mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
3943d2ff DE	430	udelay(10000);
	431	} else {
	432	/*
	433	* We have two identical banks, so the size
	434	* is twice the bank size
	435	*/
	436	size = 2 * size;
	437	}
	438	#endif
	439
62534beb	440	#ifdef CONFIG_SDRAM_ECC
3943d2ff	441	ecc_init(0, size);
62534beb SR	442	#endif
62534beb SR	443
5568e613 SR	444	/*
	445	* OK, size detected -> all done
	446	*/
088454cd SG	447	gd->ram_size = size;
	448
	449	return 0;
5568e613 SR	450	}
	451	}
	452
088454cd	453	return -ENXIO; /* nothing found ! */
5568e613 SR	454	}
	455
	456	#endif /* CONFIG_440 */
	457
c609719b	458	#endif /* CONFIG_SDRAM_BANK0 */