projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e7fb6ea | 1 | /* |
| 00cdb4ce SR |
2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
| 6 | * | |
| 3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 00cdb4ce | 8 | */ |
| 6e7fb6ea SR |
9 | |
| 10 | #include <ppc_asm.tmpl> | |
| 11 | #include <config.h> | |
| 61f2b38a | 12 | #include <asm/mmu.h> |
| 550650dd | 13 | #include <asm/ppc4xx.h> |
| 6e7fb6ea SR |
14 | |
| 15 | /************************************************************************** | |
| 16 | * TLB TABLE | |
| 17 | * | |
| 18 | * This table is used by the cpu boot code to setup the initial tlb | |
| 19 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 20 | * this table lets each board set things up however they like. | |
| 21 | * | |
| 22 | * Pointer to the table is returned in r1 | |
| 23 | * | |
| 24 | *************************************************************************/ | |
| 25 | ||
| 00cdb4ce SR |
26 | .section .bootpg,"ax" |
| 27 | .globl tlbtab | |
| 6e7fb6ea SR |
28 | |
| 29 | tlbtab: | |
| 00cdb4ce SR |
30 | tlbtab_start |
| 31 | ||
| 32 | /* | |
| 33 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
| 34 | * speed up boot process. It is patched after relocation to enable SA_I | |
| 35 | */ | |
| cf6eb6da | 36 | tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) |
| 00cdb4ce | 37 | |
| cf6eb6da SR |
38 | tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) |
| 39 | tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) | |
| 40 | tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) | |
| 41 | tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) | |
| 42 | tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) | |
| 00cdb4ce SR |
43 | |
| 44 | /* | |
| 45 | * TLB entries for SDRAM are not needed on this platform. | |
| 46 | * They are dynamically generated in the SPD DDR(2) detection | |
| 47 | * routine. | |
| 48 | */ | |
| 49 | ||
| 50 | /* internal ram (l2 cache) */ | |
| cf6eb6da | 51 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) |
| 00cdb4ce SR |
52 | |
| 53 | /* peripherals at f0000000 */ | |
| cf6eb6da | 54 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) |
| 00cdb4ce SR |
55 | |
| 56 | /* PCI */ | |
| cf6eb6da SR |
57 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) |
| 58 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) | |
| 00cdb4ce | 59 | tlbtab_end |