projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 887e2ec9 | 1 | /* |
| 02388983 SR |
2 | * (C) Copyright 2006 |
| 3 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com | |
| 4 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
| 5 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com | |
| 6 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
| 7 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com | |
| 8 | * | |
| 07b7b003 | 9 | * (C) Copyright 2006-2007 |
| 887e2ec9 SR |
10 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 11 | * | |
| 1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 887e2ec9 SR |
13 | */ |
| 14 | ||
| 02388983 SR |
15 | /* define DEBUG for debug output */ |
| 16 | #undef DEBUG | |
| 17 | ||
| 887e2ec9 SR |
18 | #include <common.h> |
| 19 | #include <asm/processor.h> | |
| 02388983 | 20 | #include <asm/io.h> |
| b36df561 | 21 | #include <asm/ppc440.h> |
| 887e2ec9 | 22 | |
| 088454cd SG |
23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | ||
| 02388983 | 25 | /*-----------------------------------------------------------------------------+ |
| ce3902e1 LJ |
26 | * Prototypes |
| 27 | *-----------------------------------------------------------------------------*/ | |
| 28 | extern int denali_wait_for_dlllock(void); | |
| 29 | extern void denali_core_search_data_eye(void); | |
| 02388983 | 30 | |
| 887e2ec9 SR |
31 | /************************************************************************* |
| 32 | * | |
| f1683aa7 | 33 | * dram_init -- 440EPx's DDR controller is a DENALI Core |
| 887e2ec9 SR |
34 | * |
| 35 | ************************************************************************/ | |
| f1683aa7 | 36 | int dram_init(void) |
| 887e2ec9 | 37 | { |
| 345b77ba | 38 | #if !defined(CONFIG_SYS_RAMBOOT) |
| 07b7b003 SR |
39 | ulong speed = get_bus_freq(0); |
| 40 | ||
| 887e2ec9 SR |
41 | mtsdram(DDR0_02, 0x00000000); |
| 42 | ||
| 887e2ec9 SR |
43 | mtsdram(DDR0_00, 0x0000190A); |
| 44 | mtsdram(DDR0_01, 0x01000000); | |
| 45 | mtsdram(DDR0_03, 0x02030602); | |
| 07b7b003 SR |
46 | mtsdram(DDR0_04, 0x0A020200); |
| 47 | mtsdram(DDR0_05, 0x02020308); | |
| 48 | mtsdram(DDR0_06, 0x0102C812); | |
| 887e2ec9 | 49 | mtsdram(DDR0_07, 0x000D0100); |
| 07b7b003 | 50 | mtsdram(DDR0_08, 0x02430001); |
| 887e2ec9 | 51 | mtsdram(DDR0_09, 0x00011D5F); |
| ee86fd15 | 52 | mtsdram(DDR0_10, 0x00000100); |
| 887e2ec9 SR |
53 | mtsdram(DDR0_11, 0x0027C800); |
| 54 | mtsdram(DDR0_12, 0x00000003); | |
| 55 | mtsdram(DDR0_14, 0x00000000); | |
| 56 | mtsdram(DDR0_17, 0x19000000); | |
| 57 | mtsdram(DDR0_18, 0x19191919); | |
| 58 | mtsdram(DDR0_19, 0x19191919); | |
| 59 | mtsdram(DDR0_20, 0x0B0B0B0B); | |
| 60 | mtsdram(DDR0_21, 0x0B0B0B0B); | |
| 61 | mtsdram(DDR0_22, 0x00267F0B); | |
| 62 | mtsdram(DDR0_23, 0x00000000); | |
| 63 | mtsdram(DDR0_24, 0x01010002); | |
| f544ff66 | 64 | if (speed > 133333334) |
| 07b7b003 SR |
65 | mtsdram(DDR0_26, 0x5B26050C); |
| 66 | else | |
| 67 | mtsdram(DDR0_26, 0x5B260408); | |
| 887e2ec9 SR |
68 | mtsdram(DDR0_27, 0x0000682B); |
| 69 | mtsdram(DDR0_28, 0x00000000); | |
| 70 | mtsdram(DDR0_31, 0x00000000); | |
| 71 | mtsdram(DDR0_42, 0x01000006); | |
| 07b7b003 SR |
72 | mtsdram(DDR0_43, 0x030A0200); |
| 73 | mtsdram(DDR0_44, 0x00000003); | |
| 887e2ec9 SR |
74 | mtsdram(DDR0_02, 0x00000001); |
| 75 | ||
| ce3902e1 | 76 | denali_wait_for_dlllock(); |
| 345b77ba | 77 | #endif /* #ifndef CONFIG_SYS_RAMBOOT */ |
| 887e2ec9 | 78 | |
| 02388983 SR |
79 | #ifdef CONFIG_DDR_DATA_EYE |
| 80 | /* -----------------------------------------------------------+ | |
| 81 | * Perform data eye search if requested. | |
| 82 | * ----------------------------------------------------------*/ | |
| ce3902e1 | 83 | denali_core_search_data_eye(); |
| 02388983 SR |
84 | #endif |
| 85 | ||
| d5a163d6 SR |
86 | /* |
| 87 | * Clear possible errors resulting from data-eye-search. | |
| 88 | * If not done, then we could get an interrupt later on when | |
| 89 | * exceptions are enabled. | |
| 90 | */ | |
| 91 | set_mcsr(get_mcsr()); | |
| 92 | ||
| 088454cd SG |
93 | gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; |
| 94 | ||
| 95 | return 0; | |
| 887e2ec9 | 96 | } |