]> git.ipfire.org Git - u-boot.git/blame - board/engicam/geam6ul/geam6ul.c
projects / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
engicam: Move uart mux init to SPL
[u-boot.git] / board / engicam / geam6ul / geam6ul.c
CommitLineData
a5b9f8c8
JT		 1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
08273bc2 10#include <mmc.h>
a5b9f8c8
JT		 11
12#include <asm/io.h>
13#include <asm/gpio.h>
14#include <linux/sizes.h>
15
16#include <asm/arch/clock.h>
084cbb60 17#include <asm/arch/crm_regs.h>
a5b9f8c8
JT		 18#include <asm/arch/iomux.h>
19#include <asm/arch/mx6-pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/imx-common/iomux-v3.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
084cbb60
JT		 25#ifdef CONFIG_NAND_MXS
26
27#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
28#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
29 PAD_CTL_SRE_FAST)
30#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
31
32static iomux_v3_cfg_t const nand_pads[] = {
33 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
34 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
35 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
36 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
37 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
38 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
39 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
40 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
41 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
42 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
43 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
44 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
45 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
46 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
47 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
48};
49
50static void setup_gpmi_nand(void)
51{
52 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
53
54 /* config gpmi nand iomux */
55 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
56
57 clrbits_le32(&mxc_ccm->CCGR4,
58 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
59 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
60 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
62 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
63
64 /*
65 * config gpmi and bch clock to 100 MHz
66 * bch/gpmi select PLL2 PFD2 400M
67 * 100M = 400M / 4
68 */
69 clrbits_le32(&mxc_ccm->cscmr1,
70 MXC_CCM_CSCMR1_BCH_CLK_SEL |
71 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
72 clrsetbits_le32(&mxc_ccm->cscdr1,
73 MXC_CCM_CSCDR1_BCH_PODF_MASK |
74 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
75 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
76 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
77
78 /* enable gpmi and bch clock gating */
79 setbits_le32(&mxc_ccm->CCGR4,
80 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
81 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
82 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
83 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
84 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
85
86 /* enable apbh clock gating */
87 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
88}
89#endif /* CONFIG_NAND_MXS */
90
08273bc2
JT		 91#ifdef CONFIG_ENV_IS_IN_MMC
92static void mmc_late_init(void)
93{
94 char cmd[32];
95 char mmcblk[32];
96 u32 dev_no = mmc_get_env_dev();
97
98 setenv_ulong("mmcdev", dev_no);
99
100 /* Set mmcblk env */
101 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
102 setenv("mmcroot", mmcblk);
103
104 sprintf(cmd, "mmc dev %d", dev_no);
105 run_command(cmd, 0);
106}
107#endif
108
9786496c
JT		 109int board_late_init(void)
110{
111 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
112 IMX6_BMODE_SHIFT) {
113 case IMX6_BMODE_SD:
114 case IMX6_BMODE_ESD:
08273bc2
JT		 115#ifdef CONFIG_ENV_IS_IN_MMC
116 mmc_late_init();
117#endif
9786496c
JT		 118 setenv("modeboot", "mmcboot");
119 break;
120 case IMX6_BMODE_NAND:
121 setenv("modeboot", "nandboot");
122 break;
123 default:
124 setenv("modeboot", "");
125 break;
126 }
127
6f1f3f59
JT		 128 if (is_mx6ul())
129 setenv("fdt_file", "imx6ul-geam-kit.dtb");
130
9786496c
JT		 131 return 0;
132}
133
a5b9f8c8
JT		 134int board_init(void)
135{
136 /* Address of boot parameters */
137 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
138
084cbb60
JT		 139#ifdef CONFIG_NAND_MXS
140 setup_gpmi_nand();
141#endif
142
a5b9f8c8
JT		 143 return 0;
144}
145
146int dram_init(void)
147{
148 gd->ram_size = imx_ddr_size();
149
150 return 0;
151}
152
153#ifdef CONFIG_SPL_BUILD
154#include <libfdt.h>
155#include <spl.h>
156
157#include <asm/arch/crm_regs.h>
158#include <asm/arch/mx6-ddr.h>
159
b805b174
JT		 160#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
161 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
162 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
163
164static iomux_v3_cfg_t const uart1_pads[] = {
165 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
166 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
167};
168
a5b9f8c8
JT		 169/* MMC board initialization is needed till adding DM support in SPL */
170#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
171#include <mmc.h>
172#include <fsl_esdhc.h>
173
174#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
175 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
176 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
177
178static iomux_v3_cfg_t const usdhc1_pads[] = {
179 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185
186 /* VSELECT */
187 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 /* CD */
189 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
190 /* RST_B */
191 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
192};
193
194#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
195
196struct fsl_esdhc_cfg usdhc_cfg[1] = {
197 {USDHC1_BASE_ADDR, 0, 4},
198};
199
200int board_mmc_getcd(struct mmc *mmc)
201{
202 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
203 int ret = 0;
204
205 switch (cfg->esdhc_base) {
206 case USDHC1_BASE_ADDR:
207 ret = !gpio_get_value(USDHC1_CD_GPIO);
208 break;
209 }
210
211 return ret;
212}
213
214int board_mmc_init(bd_t *bis)
215{
216 int i, ret;
217
218 /*
219 * According to the board_mmc_init() the following map is done:
220 * (U-boot device node) (Physical Port)
221 * mmc0 USDHC1
222 */
223 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
224 switch (i) {
225 case 0:
226 imx_iomux_v3_setup_multiple_pads(
227 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
228 gpio_direction_input(USDHC1_CD_GPIO);
229 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
230 break;
231 default:
232 printf("Warning - USDHC%d controller not supporting\n",
233 i + 1);
234 return 0;
235 }
236
237 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
238 if (ret) {
239 printf("Warning: failed to initialize mmc dev %d\n", i);
240 return ret;
241 }
242 }
243
244 return 0;
245}
246#endif /* CONFIG_FSL_ESDHC */
247
248static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
249 .grp_addds = 0x00000030,
250 .grp_ddrmode_ctl = 0x00020000,
251 .grp_b0ds = 0x00000030,
252 .grp_ctlds = 0x00000030,
253 .grp_b1ds = 0x00000030,
254 .grp_ddrpke = 0x00000000,
255 .grp_ddrmode = 0x00020000,
256 .grp_ddr_type = 0x000c0000,
257};
258
259static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
260 .dram_dqm0 = 0x00000030,
261 .dram_dqm1 = 0x00000030,
262 .dram_ras = 0x00000030,
263 .dram_cas = 0x00000030,
264 .dram_odt0 = 0x00000030,
265 .dram_odt1 = 0x00000030,
266 .dram_sdba2 = 0x00000000,
267 .dram_sdclk_0 = 0x00000008,
268 .dram_sdqs0 = 0x00000038,
269 .dram_sdqs1 = 0x00000030,
270 .dram_reset = 0x00000030,
271};
272
273static struct mx6_mmdc_calibration mx6_mmcd_calib = {
274 .p0_mpwldectrl0 = 0x00070007,
275 .p0_mpdgctrl0 = 0x41490145,
276 .p0_mprddlctl = 0x40404546,
277 .p0_mpwrdlctl = 0x4040524D,
278};
279
280struct mx6_ddr_sysinfo ddr_sysinfo = {
281 .dsize = 0,
282 .cs_density = 20,
283 .ncs = 1,
284 .cs1_mirror = 0,
285 .rtt_wr = 2,
286 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
287 .walat = 1, /* Write additional latency */
288 .ralat = 5, /* Read additional latency */
289 .mif3_mode = 3, /* Command prediction working mode */
290 .bi_on = 1, /* Bank interleaving enabled */
291 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
292 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
293 .ddr_type = DDR_TYPE_DDR3,
294};
295
296static struct mx6_ddr3_cfg mem_ddr = {
297 .mem_speed = 800,
298 .density = 4,
299 .width = 16,
300 .banks = 8,
301 .rowaddr = 13,
302 .coladdr = 10,
303 .pagesz = 2,
304 .trcd = 1375,
305 .trcmin = 4875,
306 .trasmin = 3500,
307};
308
309static void ccgr_init(void)
310{
311 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
312
313 writel(0xFFFFFFFF, &ccm->CCGR0);
314 writel(0xFFFFFFFF, &ccm->CCGR1);
315 writel(0xFFFFFFFF, &ccm->CCGR2);
316 writel(0xFFFFFFFF, &ccm->CCGR3);
317 writel(0xFFFFFFFF, &ccm->CCGR4);
318 writel(0xFFFFFFFF, &ccm->CCGR5);
319 writel(0xFFFFFFFF, &ccm->CCGR6);
320 writel(0xFFFFFFFF, &ccm->CCGR7);
321}
322
323static void spl_dram_init(void)
324{
325 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
326 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
327}
328
329void board_init_f(ulong dummy)
330{
331 /* setup AIPS and disable watchdog */
332 arch_cpu_init();
333
334 ccgr_init();
335
336 /* iomux and setup of i2c */
b805b174 337 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
a5b9f8c8
JT		 338
339 /* setup GP timer */
340 timer_init();
341
342 /* UART clocks enabled and gd valid - init serial console */
343 preloader_console_init();
344
345 /* DDR initialization */
346 spl_dram_init();
347
348 /* Clear the BSS. */
349 memset(__bss_start, 0, __bss_end - __bss_start);
350
351 /* load/boot image from boot device */
352 board_init_r(NULL, 0);
353}
354#endif /* CONFIG_SPL_BUILD */
"Das U-Boot" Source Tree