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Commit | Line | Data |
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2da0fc0d DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
2da0fc0d DE |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/ppc4xx-gpio.h> | |
13 | ||
6e9e6c36 | 14 | #include "405ep.h" |
2da0fc0d DE |
15 | #include <gdsys_fpga.h> |
16 | ||
17 | #include "../common/osd.h" | |
18 | ||
6e9e6c36 DE |
19 | #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) |
20 | #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) | |
b9ab8a99 | 21 | #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) |
5cb4100f DE |
22 | #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) |
23 | ||
6e9e6c36 DE |
24 | #define LATCH2_MC2_PRESENT_N 0x0080 |
25 | ||
2da0fc0d | 26 | enum { |
e1d1127a DE |
27 | UNITTYPE_MAIN = 1<<0, |
28 | UNITTYPE_SERVER = 1<<1, | |
29 | UNITTYPE_DISPLAYPORT = 1<<2, | |
2da0fc0d DE |
30 | }; |
31 | ||
32 | enum { | |
33 | HWVER_101 = 0, | |
34 | HWVER_110 = 1, | |
e1d1127a DE |
35 | HWVER_130 = 2, |
36 | HWVER_140 = 3, | |
37 | HWVER_150 = 4, | |
38 | HWVER_160 = 5, | |
39 | HWVER_170 = 6, | |
2da0fc0d DE |
40 | }; |
41 | ||
42 | enum { | |
43 | AUDIO_NONE = 0, | |
44 | AUDIO_TX = 1, | |
45 | AUDIO_RX = 2, | |
46 | AUDIO_RXTX = 3, | |
47 | }; | |
48 | ||
49 | enum { | |
50 | SYSCLK_156250 = 2, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | RAM_NONE = 0, | |
55 | RAM_DDR2_32 = 1, | |
56 | RAM_DDR2_64 = 2, | |
57 | }; | |
58 | ||
aba27acf DE |
59 | struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; |
60 | ||
b19bf834 DE |
61 | int misc_init_r(void) |
62 | { | |
853eaa4f SG |
63 | /* |
64 | * Note: DTT has been removed. Please use UCLASS_THERMAL. | |
65 | * | |
66 | * startup fans | |
67 | * | |
68 | * dtt_init(); | |
69 | */ | |
b19bf834 DE |
70 | |
71 | return 0; | |
72 | } | |
73 | ||
5cb4100f DE |
74 | static unsigned int get_hwver(void) |
75 | { | |
76 | u16 latch3 = in_le16((void *)LATCH3_BASE); | |
77 | ||
78 | return latch3 & 0x0003; | |
79 | } | |
80 | ||
81 | static unsigned int get_mc2_present(void) | |
82 | { | |
83 | u16 latch2 = in_le16((void *)LATCH2_BASE); | |
84 | ||
85 | return !(latch2 & LATCH2_MC2_PRESENT_N); | |
86 | } | |
87 | ||
2da0fc0d DE |
88 | static void print_fpga_info(unsigned dev) |
89 | { | |
aba27acf DE |
90 | u16 versions; |
91 | u16 fpga_version; | |
92 | u16 fpga_features; | |
2da0fc0d DE |
93 | unsigned unit_type; |
94 | unsigned hardware_version; | |
2da0fc0d DE |
95 | unsigned feature_rs232; |
96 | unsigned feature_audio; | |
97 | unsigned feature_sysclock; | |
98 | unsigned feature_ramconfig; | |
99 | unsigned feature_carrier_speed; | |
100 | unsigned feature_carriers; | |
101 | unsigned feature_video_channels; | |
102 | int fpga_state = get_fpga_state(dev); | |
103 | ||
104 | printf("FPGA%d: ", dev); | |
105 | ||
aba27acf DE |
106 | FPGA_GET_REG(dev, versions, &versions); |
107 | FPGA_GET_REG(dev, fpga_version, &fpga_version); | |
108 | FPGA_GET_REG(dev, fpga_features, &fpga_features); | |
109 | ||
2da0fc0d DE |
110 | hardware_version = versions & 0x000f; |
111 | ||
112 | if (fpga_state | |
113 | && !((hardware_version == HWVER_101) | |
114 | && (fpga_state == FPGA_STATE_DONE_FAILED))) { | |
115 | puts("not available\n"); | |
473c0abe TR |
116 | if (fpga_state & FPGA_STATE_DONE_FAILED) |
117 | puts(" Waiting for FPGA-DONE timed out.\n"); | |
118 | if (fpga_state & FPGA_STATE_REFLECTION_FAILED) | |
119 | puts(" FPGA reflection test failed.\n"); | |
2da0fc0d DE |
120 | return; |
121 | } | |
122 | ||
123 | unit_type = (versions >> 4) & 0x000f; | |
124 | hardware_version = versions & 0x000f; | |
2da0fc0d DE |
125 | feature_rs232 = fpga_features & (1<<11); |
126 | feature_audio = (fpga_features >> 9) & 0x0003; | |
127 | feature_sysclock = (fpga_features >> 7) & 0x0003; | |
128 | feature_ramconfig = (fpga_features >> 5) & 0x0003; | |
129 | feature_carrier_speed = fpga_features & (1<<4); | |
130 | feature_carriers = (fpga_features >> 2) & 0x0003; | |
131 | feature_video_channels = fpga_features & 0x0003; | |
132 | ||
e1d1127a DE |
133 | if (unit_type & UNITTYPE_MAIN) |
134 | printf("Mainchannel "); | |
135 | else | |
136 | printf("Videochannel "); | |
2da0fc0d | 137 | |
e1d1127a DE |
138 | if (unit_type & UNITTYPE_SERVER) |
139 | printf("Serverside "); | |
140 | else | |
141 | printf("Userside "); | |
142 | ||
143 | if (unit_type & UNITTYPE_DISPLAYPORT) | |
144 | printf("DisplayPort"); | |
145 | else | |
146 | printf("DVI-DL"); | |
2da0fc0d | 147 | |
e1d1127a DE |
148 | switch (hardware_version) { |
149 | case HWVER_101: | |
150 | printf(" HW-Ver 1.01\n"); | |
2da0fc0d DE |
151 | break; |
152 | ||
e1d1127a DE |
153 | case HWVER_110: |
154 | printf(" HW-Ver 1.10-1.20\n"); | |
2da0fc0d DE |
155 | break; |
156 | ||
e1d1127a DE |
157 | case HWVER_130: |
158 | printf(" HW-Ver 1.30\n"); | |
2da0fc0d | 159 | break; |
2da0fc0d | 160 | |
e1d1127a DE |
161 | case HWVER_140: |
162 | printf(" HW-Ver 1.40-1.43\n"); | |
2da0fc0d DE |
163 | break; |
164 | ||
e1d1127a DE |
165 | case HWVER_150: |
166 | printf(" HW-Ver 1.50\n"); | |
2ade7bee DE |
167 | break; |
168 | ||
e1d1127a DE |
169 | case HWVER_160: |
170 | printf(" HW-Ver 1.60-1.61\n"); | |
2ade7bee DE |
171 | break; |
172 | ||
e1d1127a DE |
173 | case HWVER_170: |
174 | printf(" HW-Ver 1.70\n"); | |
2da0fc0d DE |
175 | break; |
176 | ||
177 | default: | |
178 | printf(" HW-Ver %d(not supported)\n", | |
179 | hardware_version); | |
180 | break; | |
181 | } | |
182 | ||
183 | printf(" FPGA V %d.%02d, features:", | |
184 | fpga_version / 100, fpga_version % 100); | |
185 | ||
186 | printf(" %sRS232", feature_rs232 ? "" : "no "); | |
187 | ||
188 | switch (feature_audio) { | |
189 | case AUDIO_NONE: | |
190 | printf(", no audio"); | |
191 | break; | |
192 | ||
193 | case AUDIO_TX: | |
194 | printf(", audio tx"); | |
195 | break; | |
196 | ||
197 | case AUDIO_RX: | |
198 | printf(", audio rx"); | |
199 | break; | |
200 | ||
201 | case AUDIO_RXTX: | |
202 | printf(", audio rx+tx"); | |
203 | break; | |
204 | ||
205 | default: | |
206 | printf(", audio %d(not supported)", feature_audio); | |
207 | break; | |
208 | } | |
209 | ||
210 | switch (feature_sysclock) { | |
211 | case SYSCLK_156250: | |
212 | printf(", clock 156.25 MHz"); | |
213 | break; | |
214 | ||
215 | default: | |
216 | printf(", clock %d(not supported)", feature_sysclock); | |
217 | break; | |
218 | } | |
219 | ||
220 | puts(",\n "); | |
221 | ||
222 | switch (feature_ramconfig) { | |
223 | case RAM_NONE: | |
224 | printf("no RAM"); | |
225 | break; | |
226 | ||
227 | case RAM_DDR2_32: | |
228 | printf("RAM 32 bit DDR2"); | |
229 | break; | |
230 | ||
231 | case RAM_DDR2_64: | |
232 | printf("RAM 64 bit DDR2"); | |
233 | break; | |
234 | ||
235 | default: | |
236 | printf("RAM %d(not supported)", feature_ramconfig); | |
237 | break; | |
238 | } | |
239 | ||
240 | printf(", %d carrier(s) %s", feature_carriers, | |
241 | feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); | |
242 | ||
243 | printf(", %d video channel(s)\n", feature_video_channels); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Check Board Identity: | |
248 | */ | |
249 | int checkboard(void) | |
250 | { | |
b19bf834 | 251 | char *s = getenv("serial#"); |
2da0fc0d | 252 | |
b19bf834 | 253 | puts("Board: "); |
2da0fc0d | 254 | |
b19bf834 | 255 | puts("DLVision 10G"); |
2da0fc0d | 256 | |
b19bf834 | 257 | if (s != NULL) { |
2da0fc0d | 258 | puts(", serial# "); |
b19bf834 | 259 | puts(s); |
2da0fc0d DE |
260 | } |
261 | ||
262 | puts("\n"); | |
263 | ||
2da0fc0d DE |
264 | return 0; |
265 | } | |
266 | ||
267 | int last_stage_init(void) | |
268 | { | |
aba27acf DE |
269 | u16 versions; |
270 | ||
271 | FPGA_GET_REG(0, versions, &versions); | |
b9ab8a99 | 272 | |
b19bf834 DE |
273 | print_fpga_info(0); |
274 | if (get_mc2_present()) | |
275 | print_fpga_info(1); | |
276 | ||
e1d1127a | 277 | if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER) |
b9ab8a99 DE |
278 | return 0; |
279 | ||
5cb4100f | 280 | if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) |
b9ab8a99 | 281 | osd_probe(0); |
2da0fc0d | 282 | |
5cb4100f DE |
283 | if (get_mc2_present() && |
284 | (!get_fpga_state(1) || (get_hwver() == HWVER_101))) | |
b9ab8a99 | 285 | osd_probe(1); |
2da0fc0d DE |
286 | |
287 | return 0; | |
288 | } | |
6e9e6c36 DE |
289 | |
290 | void gd405ep_init(void) | |
291 | { | |
292 | } | |
293 | ||
294 | void gd405ep_set_fpga_reset(unsigned state) | |
295 | { | |
296 | if (state) { | |
297 | out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); | |
298 | out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); | |
299 | } else { | |
300 | out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); | |
301 | out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); | |
302 | } | |
303 | } | |
304 | ||
305 | void gd405ep_setup_hw(void) | |
306 | { | |
307 | /* | |
308 | * set "startup-finished"-gpios | |
309 | */ | |
310 | gpio_write_bit(21, 0); | |
311 | gpio_write_bit(22, 1); | |
312 | } | |
313 | ||
314 | int gd405ep_get_fpga_done(unsigned fpga) | |
315 | { | |
316 | return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); | |
317 | } |