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8e429b3e SP |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
8e429b3e SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
6 | * Configuation settings for the AT91SAM9263EK board. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
8e429b3e SP |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
cd46b0f2 XH |
14 | /* |
15 | * SoC must be defined first, before hardware.h is included. | |
16 | * In this case SoC is defined in boards.cfg. | |
17 | */ | |
18 | #include <asm/hardware.h> | |
19 | ||
8e429b3e | 20 | /* ARM asynchronous clock */ |
cd46b0f2 XH |
21 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
22 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
cd46b0f2 XH |
23 | |
24 | #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ | |
8e429b3e | 25 | |
dc39ae95 | 26 | #define CONFIG_ARCH_CPU_INIT |
8e429b3e SP |
27 | |
28 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
29 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
30 | #define CONFIG_INITRD_TAG 1 | |
31 | ||
1b3b7c64 | 32 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
8e429b3e | 33 | #define CONFIG_SKIP_LOWLEVEL_INIT |
cd46b0f2 XH |
34 | #else |
35 | #define CONFIG_SYS_USE_NORFLASH | |
1b3b7c64 | 36 | #endif |
8e429b3e SP |
37 | |
38 | /* | |
39 | * Hardware drivers | |
40 | */ | |
cd46b0f2 | 41 | #define CONFIG_ATMEL_LEGACY |
8e429b3e | 42 | |
56a2479c | 43 | /* LCD */ |
56a2479c SP |
44 | #define LCD_BPP LCD_COLOR8 |
45 | #define CONFIG_LCD_LOGO 1 | |
46 | #undef LCD_TEST_PATTERN | |
47 | #define CONFIG_LCD_INFO 1 | |
48 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
56a2479c SP |
49 | #define CONFIG_ATMEL_LCD 1 |
50 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
56a2479c | 51 | |
8e429b3e SP |
52 | /* |
53 | * BOOTP options | |
54 | */ | |
55 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
8e429b3e | 56 | |
8e429b3e SP |
57 | /* SDRAM */ |
58 | #define CONFIG_NR_DRAM_BANKS 1 | |
cd46b0f2 XH |
59 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
60 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
61 | ||
62 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
0b8908f9 | 63 | (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
8e429b3e | 64 | |
8e429b3e | 65 | /* NOR flash, if populated */ |
1b3b7c64 | 66 | #ifdef CONFIG_SYS_USE_NORFLASH |
6d0f6bcf | 67 | #define CONFIG_SYS_FLASH_CFI 1 |
1b3b7c64 JCPV |
68 | #define CONFIG_FLASH_CFI_DRIVER 1 |
69 | #define PHYS_FLASH_1 0x10000000 | |
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
71 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
72 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
1b3b7c64 JCPV |
73 | |
74 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 | |
75 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
76 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
5e7d0917 | 77 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) |
1b3b7c64 JCPV |
78 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) |
79 | ||
80 | /* Address and size of Primary Environment Sector */ | |
5e7d0917 | 81 | #define CONFIG_ENV_SIZE 0x10000 |
1b3b7c64 | 82 | |
1b3b7c64 | 83 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
93ea89f0 | 84 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
1b3b7c64 JCPV |
85 | "update=" \ |
86 | "protect off ${monitor_base} +${filesize};" \ | |
87 | "erase ${monitor_base} +${filesize};" \ | |
88461f16 | 88 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ |
1b3b7c64 JCPV |
89 | "protect on ${monitor_base} +${filesize}\0" |
90 | ||
91 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
92 | #define MASTER_PLL_MUL 171 | |
93 | #define MASTER_PLL_DIV 14 | |
1b34f00c | 94 | #define MASTER_PLL_OUT 3 |
1b3b7c64 JCPV |
95 | |
96 | /* clocks */ | |
97 | #define CONFIG_SYS_MOR_VAL \ | |
1b34f00c JS |
98 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
99 | #define CONFIG_SYS_PLLAR_VAL \ | |
100 | (AT91_PMC_PLLAR_29 | \ | |
101 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ | |
102 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ | |
103 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ | |
104 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) | |
1b3b7c64 JCPV |
105 | |
106 | /* PCK/2 = MCK Master Clock from PLLA */ | |
107 | #define CONFIG_SYS_MCKR1_VAL \ | |
1b34f00c JS |
108 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
109 | AT91_PMC_MCKR_MDIV_2) | |
110 | ||
1b3b7c64 JCPV |
111 | /* PCK/2 = MCK Master Clock from PLLA */ |
112 | #define CONFIG_SYS_MCKR2_VAL \ | |
1b34f00c JS |
113 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
114 | AT91_PMC_MCKR_MDIV_2) | |
1b3b7c64 JCPV |
115 | |
116 | /* define PDC[31:16] as DATA[31:16] */ | |
117 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | |
118 | /* no pull-up for D[31:16] */ | |
119 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | |
120 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | |
1b34f00c JS |
121 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
122 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ | |
123 | AT91_MATRIX_CSA_EBI_CS1A) | |
1b3b7c64 JCPV |
124 | |
125 | /* SDRAM */ | |
126 | /* SDRAMC_MR Mode register */ | |
127 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | |
128 | /* SDRAMC_TR - Refresh Timer register */ | |
129 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | |
130 | /* SDRAMC_CR - Configuration register*/ | |
131 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
132 | (AT91_SDRAMC_NC_9 | \ | |
133 | AT91_SDRAMC_NR_13 | \ | |
134 | AT91_SDRAMC_NB_4 | \ | |
135 | AT91_SDRAMC_CAS_3 | \ | |
136 | AT91_SDRAMC_DBW_32 | \ | |
137 | (1 << 8) | /* Write Recovery Delay */ \ | |
138 | (7 << 12) | /* Row Cycle Delay */ \ | |
139 | (2 << 16) | /* Row Precharge Delay */ \ | |
140 | (2 << 20) | /* Row to Column Delay */ \ | |
141 | (5 << 24) | /* Active to Precharge Delay */ \ | |
142 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | |
143 | ||
144 | /* Memory Device Register -> SDRAM */ | |
145 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
146 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
147 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
148 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
149 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
150 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
151 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
152 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
153 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
154 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
155 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
156 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
157 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
158 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
159 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
160 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
161 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
162 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
163 | ||
164 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
1b34f00c JS |
165 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
166 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ | |
167 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
168 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ | |
169 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ | |
170 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
1b3b7c64 | 171 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
1b34f00c | 172 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
1b3b7c64 | 173 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
1b34f00c JS |
174 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
175 | AT91_SMC_MODE_DBW_16 | \ | |
176 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) | |
1b3b7c64 JCPV |
177 | |
178 | /* user reset enable */ | |
179 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
180 | (AT91_RSTC_KEY | \ | |
1b34f00c JS |
181 | AT91_RSTC_MR_URSTEN | \ |
182 | AT91_RSTC_MR_ERSTL(15)) | |
1b3b7c64 JCPV |
183 | |
184 | /* Disable Watchdog */ | |
185 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
1b34f00c JS |
186 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
187 | AT91_WDT_MR_WDV(0xfff) | \ | |
188 | AT91_WDT_MR_WDDIS | \ | |
189 | AT91_WDT_MR_WDD(0xfff)) | |
190 | ||
1b3b7c64 | 191 | #endif |
8e429b3e SP |
192 | #endif |
193 | ||
194 | /* NAND flash */ | |
74c076d6 JCPV |
195 | #ifdef CONFIG_CMD_NAND |
196 | #define CONFIG_NAND_ATMEL | |
6d0f6bcf | 197 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
cd46b0f2 | 198 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
6d0f6bcf | 199 | #define CONFIG_SYS_NAND_DBW_8 1 |
74c076d6 JCPV |
200 | /* our ALE is AD21 */ |
201 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
202 | /* our CLE is AD22 */ | |
203 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
cd46b0f2 XH |
204 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 |
205 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 | |
74c076d6 | 206 | #endif |
8e429b3e SP |
207 | |
208 | /* Ethernet */ | |
8e429b3e | 209 | #define CONFIG_RESET_PHY_R 1 |
4535a24c | 210 | #define CONFIG_AT91_WANTS_COMMON_PHY |
8e429b3e SP |
211 | |
212 | /* USB */ | |
2b7178af | 213 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 214 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
8e429b3e | 215 | #define CONFIG_USB_OHCI_NEW 1 |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
217 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
218 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | |
219 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
8e429b3e | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
8e429b3e | 222 | |
cd46b0f2 | 223 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
6d0f6bcf | 224 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
8e429b3e | 225 | |
6d0f6bcf | 226 | #ifdef CONFIG_SYS_USE_DATAFLASH |
8e429b3e SP |
227 | |
228 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
eab36f6d | 229 | #define CONFIG_ENV_OFFSET 0x4200 |
0e8d1586 | 230 | #define CONFIG_ENV_SIZE 0x4200 |
eab36f6d WY |
231 | #define CONFIG_ENV_SECT_SIZE 0x210 |
232 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 | |
233 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ | |
234 | "sf read 0x22000000 0x84000 0x294000; " \ | |
235 | "bootm 0x22000000" | |
8e429b3e | 236 | |
1b3b7c64 | 237 | #elif CONFIG_SYS_USE_NANDFLASH |
8e429b3e SP |
238 | |
239 | /* bootstrap + u-boot + env + linux in nandflash */ | |
0b8908f9 | 240 | #define CONFIG_ENV_OFFSET 0x120000 |
0c58cfa9 | 241 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
0e8d1586 | 242 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
0c58cfa9 | 243 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
8e429b3e SP |
244 | #endif |
245 | ||
8e429b3e SP |
246 | /* |
247 | * Size of malloc() pool | |
248 | */ | |
cd46b0f2 | 249 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
8e429b3e | 250 | |
8e429b3e | 251 | #endif |