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4745acaa SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4745acaa SR |
8 | */ |
9 | ||
10 | /************************************************************************ | |
11 | * katmai.h - configuration for AMCC Katmai (440SPe) | |
12 | ***********************************************************************/ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
83b4cfa3 | 16 | |
4745acaa SR |
17 | /*----------------------------------------------------------------------- |
18 | * High Level Configuration Options | |
19 | *----------------------------------------------------------------------*/ | |
20 | #define CONFIG_KATMAI 1 /* Board is Katmai */ | |
4745acaa SR |
21 | #define CONFIG_440 1 /* ... PPC440 family */ |
22 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
2a72e9ed | 23 | #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ |
4745acaa | 24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
6d0f6bcf | 25 | #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
490f2040 | 26 | |
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
28 | ||
5d812b8b SR |
29 | /* |
30 | * Enable this board for more than 2GB of SDRAM | |
31 | */ | |
5d812b8b | 32 | #define CONFIG_VERY_BIG_RAM |
5d812b8b | 33 | |
490f2040 SR |
34 | /* |
35 | * Include common defines/options for all AMCC eval boards | |
36 | */ | |
37 | #define CONFIG_HOSTNAME katmai | |
38 | #include "amcc-common.h" | |
4745acaa | 39 | |
4745acaa SR |
40 | #undef CONFIG_SHOW_BOOT_PROGRESS |
41 | ||
42 | /*----------------------------------------------------------------------- | |
43 | * Base addresses -- Note these are effective addresses where the | |
44 | * actual resources get mapped (not physical addresses) | |
45 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 46 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ |
6d0f6bcf | 47 | #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ |
4745acaa | 48 | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ |
50 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
51 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE | |
4745acaa | 52 | |
6d0f6bcf JCPV |
53 | #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ |
54 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ | |
55 | #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ | |
4745acaa | 56 | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 |
58 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 | |
59 | #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 | |
60 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 | |
61 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 | |
62 | #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 | |
4745acaa | 63 | |
97923770 | 64 | /* base address of inbound PCIe window */ |
6d0f6bcf | 65 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL |
97923770 | 66 | |
4745acaa | 67 | /* System RAM mapped to PCI space */ |
6d0f6bcf JCPV |
68 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE |
69 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE | |
4745acaa SR |
70 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) |
71 | ||
6d0f6bcf | 72 | #define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ |
4745acaa SR |
73 | |
74 | /*----------------------------------------------------------------------- | |
75 | * Initial RAM & stack pointer (placed in internal SRAM) | |
76 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
78 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
79 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
553f0982 | 80 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
4745acaa | 81 | |
25ddd1fb | 82 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 83 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
4745acaa SR |
84 | |
85 | /*----------------------------------------------------------------------- | |
86 | * Serial Port | |
87 | *----------------------------------------------------------------------*/ | |
550650dd | 88 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
4745acaa SR |
90 | |
91 | /*----------------------------------------------------------------------- | |
92 | * DDR SDRAM | |
93 | *----------------------------------------------------------------------*/ | |
94 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ | |
ba58e4c9 | 95 | #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ |
2721a68a | 96 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
845c6c95 | 97 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/ |
4745acaa | 98 | #undef CONFIG_STRESS |
4745acaa SR |
99 | |
100 | /*----------------------------------------------------------------------- | |
101 | * I2C | |
102 | *----------------------------------------------------------------------*/ | |
880540de | 103 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
4745acaa | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ |
4745acaa SR |
106 | |
107 | #define IIC0_BOOTPROM_ADDR 0x50 | |
108 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 | |
109 | ||
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50) |
111 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
112 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4745acaa | 114 | |
efe12bce SR |
115 | /* I2C bootstrap EEPROM */ |
116 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
117 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
118 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 8 | |
119 | ||
4745acaa SR |
120 | /* I2C RTC */ |
121 | #define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
123 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
124 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
4745acaa | 125 | |
4745acaa SR |
126 | /*----------------------------------------------------------------------- |
127 | * Environment | |
128 | *----------------------------------------------------------------------*/ | |
5a1aceb0 | 129 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ |
4745acaa | 130 | |
490f2040 SR |
131 | /* |
132 | * Default environment variables | |
133 | */ | |
4745acaa | 134 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
135 | CONFIG_AMCC_DEF_ENV \ |
136 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
490f2040 | 137 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
fc21cd55 SR |
138 | "kernel_addr=ff000000\0" \ |
139 | "fdt_addr=ff1e0000\0" \ | |
140 | "ramdisk_addr=ff200000\0" \ | |
6efc1fc0 | 141 | "pciconfighost=1\0" \ |
d4cb2d17 | 142 | "pcie_mode=RP:RP:RP\0" \ |
4745acaa | 143 | "" |
079a136c | 144 | |
bc234c12 | 145 | /* |
490f2040 | 146 | * Commands additional to the ones defined in amcc-common.h |
bc234c12 | 147 | */ |
bc234c12 | 148 | #define CONFIG_CMD_PCI |
bc234c12 | 149 | #define CONFIG_CMD_SDRAM |
4745acaa SR |
150 | |
151 | #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ | |
4745acaa SR |
152 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
153 | #define CONFIG_HAS_ETH0 | |
154 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
155 | #define CONFIG_PHY_RESET_DELAY 1000 | |
156 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
157 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
4745acaa SR |
158 | |
159 | /*----------------------------------------------------------------------- | |
160 | * FLASH related | |
161 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 162 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 163 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
165 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
4745acaa | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
168 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
169 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
4745acaa | 170 | |
6d0f6bcf JCPV |
171 | #undef CONFIG_SYS_FLASH_CHECKSUM |
172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
173 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
4745acaa | 174 | |
0e8d1586 | 175 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 176 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 177 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
4745acaa SR |
178 | |
179 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
180 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
181 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
4745acaa SR |
182 | |
183 | /*----------------------------------------------------------------------- | |
184 | * PCI stuff | |
185 | *----------------------------------------------------------------------- | |
186 | */ | |
187 | /* General PCI */ | |
842033e6 | 188 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
4745acaa | 189 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
6efc1fc0 | 190 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE |
4745acaa SR |
191 | |
192 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
194 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
4745acaa | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
197 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
198 | /* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */ | |
4745acaa SR |
199 | |
200 | /* | |
201 | * NETWORK Support (PCI): | |
202 | */ | |
203 | /* Support for Intel 82557/82559/82559ER chips. */ | |
204 | #define CONFIG_EEPRO100 | |
205 | ||
206 | /*----------------------------------------------------------------------- | |
207 | * Xilinx System ACE support | |
208 | *----------------------------------------------------------------------*/ | |
209 | #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ |
211 | #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE | |
4745acaa SR |
212 | |
213 | /*----------------------------------------------------------------------- | |
214 | * External Bus Controller (EBC) Setup | |
215 | *----------------------------------------------------------------------*/ | |
216 | ||
217 | /* Memory Bank 0 (Flash) initialization */ | |
6d0f6bcf | 218 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
4745acaa SR |
219 | EBC_BXAP_TWT_ENCODE(7) | \ |
220 | EBC_BXAP_BCE_DISABLE | \ | |
221 | EBC_BXAP_BCT_2TRANS | \ | |
222 | EBC_BXAP_CSN_ENCODE(0) | \ | |
223 | EBC_BXAP_OEN_ENCODE(0) | \ | |
224 | EBC_BXAP_WBN_ENCODE(0) | \ | |
225 | EBC_BXAP_WBF_ENCODE(0) | \ | |
226 | EBC_BXAP_TH_ENCODE(0) | \ | |
227 | EBC_BXAP_RE_DISABLED | \ | |
228 | EBC_BXAP_SOR_DELAYED | \ | |
229 | EBC_BXAP_BEM_WRITEONLY | \ | |
230 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf | 231 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ |
4745acaa SR |
232 | EBC_BXCR_BS_16MB | \ |
233 | EBC_BXCR_BU_RW | \ | |
234 | EBC_BXCR_BW_16BIT) | |
235 | ||
236 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ |
d2168626 SR |
238 | EBC_BXAP_TWT_ENCODE(4) | \ |
239 | EBC_BXAP_BCE_DISABLE | \ | |
240 | EBC_BXAP_BCT_2TRANS | \ | |
241 | EBC_BXAP_CSN_ENCODE(0) | \ | |
242 | EBC_BXAP_OEN_ENCODE(0) | \ | |
243 | EBC_BXAP_WBN_ENCODE(0) | \ | |
244 | EBC_BXAP_WBF_ENCODE(0) | \ | |
245 | EBC_BXAP_TH_ENCODE(0) | \ | |
246 | EBC_BXAP_RE_DISABLED | \ | |
247 | EBC_BXAP_SOR_NONDELAYED | \ | |
248 | EBC_BXAP_BEM_WRITEONLY | \ | |
249 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf | 250 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \ |
4745acaa SR |
251 | EBC_BXCR_BS_1MB | \ |
252 | EBC_BXCR_BU_RW | \ | |
253 | EBC_BXCR_BW_16BIT) | |
254 | ||
255 | /*------------------------------------------------------------------------- | |
256 | * Initialize EBC CONFIG - | |
257 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
258 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
259 | *-------------------------------------------------------------------------*/ | |
6d0f6bcf | 260 | #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ |
4745acaa SR |
261 | EBC_CFG_PTD_ENABLE | \ |
262 | EBC_CFG_RTC_16PERCLK | \ | |
263 | EBC_CFG_ATC_PREVIOUS | \ | |
264 | EBC_CFG_DTC_PREVIOUS | \ | |
265 | EBC_CFG_CTC_PREVIOUS | \ | |
266 | EBC_CFG_OEO_PREVIOUS | \ | |
267 | EBC_CFG_EMC_DEFAULT | \ | |
268 | EBC_CFG_PME_DISABLE | \ | |
269 | EBC_CFG_PR_16) | |
270 | ||
ba58e4c9 SR |
271 | /*----------------------------------------------------------------------- |
272 | * GPIO Setup | |
273 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 |
275 | #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 | |
276 | #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 | |
277 | #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 | |
278 | ||
279 | #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ | |
280 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ | |
281 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ | |
282 | GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) | |
283 | #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
284 | #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
285 | #define CONFIG_SYS_GPIO_ODR 0 | |
ba58e4c9 | 286 | |
4745acaa | 287 | #endif /* __CONFIG_H */ |