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   2   Copyright 1988-2022 Free Software Foundation, Inc.
   3   This is part of the GCC manual.
   4   For copying conditions, see the copyright.rst file.
   5
   6 .. _x86-specific-memory-model-extensions-for-transactional-memory:
   7
   8 x86-Specific Memory Model Extensions for Transactional Memory
   9 *************************************************************
  10
  11 The x86 architecture supports additional memory ordering flags
  12 to mark critical sections for hardware lock elision.
  13 These must be specified in addition to an existing memory order to
  14 atomic intrinsics.
  15
  16 ``__ATOMIC_HLE_ACQUIRE``
  17   Start lock elision on a lock variable.
  18   Memory order must be ``__ATOMIC_ACQUIRE`` or stronger.
  19
  20 ``__ATOMIC_HLE_RELEASE``
  21   End lock elision on a lock variable.
  22   Memory order must be ``__ATOMIC_RELEASE`` or stronger.
  23
  24 When a lock acquire fails, it is required for good performance to abort
  25 the transaction quickly. This can be done with a ``_mm_pause``.
  26
  27 .. code-block:: c++
  28
  29   #include <immintrin.h> // For _mm_pause
  30
  31   int lockvar;
  32
  33   /* Acquire lock with lock elision */
  34   while (__atomic_exchange_n(&lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE))
  35       _mm_pause(); /* Abort failed transaction */
  36   ...
  37   /* Free lock with lock elision */
  38   __atomic_store_n(&lockvar, 0, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE);