git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 217fbbc122663c5a3dac752cebef44fb3e0cc179 Mon Sep 17 00:00:00 2001
   2 From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
   3 Date: Fri, 10 Nov 2023 14:49:35 +0530
   4 Subject: [PATCH] firmware: qcom_scm: ipq5332: add msa lock/unlock
   5  support
   6
   7 IPQ5332 user pd remoteproc firmwares need to be locked
   8 with MSA(modem secure access) features. This patch add
   9 support to lock/unlock MSA features.
  10
  11 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
  12 ---
  13  drivers/firmware/qcom_scm.c            | 78 ++++++++++++++++++++++++++
  14  drivers/firmware/qcom_scm.h            |  2 +
  15  include/linux/firmware/qcom/qcom_scm.h |  2 +
  16  3 files changed, 82 insertions(+)
  17
  18 --- a/drivers/firmware/qcom_scm.c
  19 +++ b/drivers/firmware/qcom_scm.c
  20 @@ -712,6 +712,84 @@ bool qcom_scm_pas_supported(u32 peripher
  21  }
  22  EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
  23
  24 +/**
  25 + * qcom_scm_msa_lock() - Lock given peripheral firmware region as MSA
  26 + *
  27 + * @peripheral:        peripheral id
  28 + *
  29 + * Return 0 on success.
  30 + */
  31 +int qcom_scm_msa_lock(u32 peripheral)
  32 +{
  33 +       int ret;
  34 +       struct qcom_scm_desc desc = {
  35 +               .svc = QCOM_SCM_SVC_PIL,
  36 +               .cmd = QCOM_SCM_MSA_LOCK,
  37 +               .arginfo = QCOM_SCM_ARGS(1),
  38 +               .args[0] = peripheral,
  39 +               .owner = ARM_SMCCC_OWNER_SIP,
  40 +       };
  41 +       struct qcom_scm_res res;
  42 +
  43 +       if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
  44 +                                         QCOM_SCM_MSA_LOCK))
  45 +               return 0;
  46 +
  47 +       ret = qcom_scm_clk_enable();
  48 +       if (ret)
  49 +               return ret;
  50 +
  51 +       ret = qcom_scm_bw_enable();
  52 +       if (ret)
  53 +               return ret;
  54 +
  55 +       ret = qcom_scm_call(__scm->dev, &desc, &res);
  56 +       qcom_scm_bw_disable();
  57 +       qcom_scm_clk_disable();
  58 +
  59 +       return ret ? : res.result[0];
  60 +}
  61 +EXPORT_SYMBOL_GPL(qcom_scm_msa_lock);
  62 +
  63 +/**
  64 + * qcom_scm_msa_unlock() - Unlock given peripheral MSA firmware region
  65 + *
  66 + * @peripheral:        peripheral id
  67 + *
  68 + * Return 0 on success.
  69 + */
  70 +int qcom_scm_msa_unlock(u32 peripheral)
  71 +{
  72 +       int ret;
  73 +       struct qcom_scm_desc desc = {
  74 +               .svc = QCOM_SCM_SVC_PIL,
  75 +               .cmd = QCOM_SCM_MSA_UNLOCK,
  76 +               .arginfo = QCOM_SCM_ARGS(1),
  77 +               .args[0] = peripheral,
  78 +               .owner = ARM_SMCCC_OWNER_SIP,
  79 +       };
  80 +       struct qcom_scm_res res;
  81 +
  82 +       if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
  83 +                                         QCOM_SCM_MSA_UNLOCK))
  84 +               return 0;
  85 +
  86 +       ret = qcom_scm_clk_enable();
  87 +       if (ret)
  88 +               return ret;
  89 +
  90 +       ret = qcom_scm_bw_enable();
  91 +       if (ret)
  92 +               return ret;
  93 +
  94 +       ret = qcom_scm_call(__scm->dev, &desc, &res);
  95 +       qcom_scm_bw_disable();
  96 +       qcom_scm_clk_disable();
  97 +
  98 +       return ret ? : res.result[0];
  99 +}
 100 +EXPORT_SYMBOL_GPL(qcom_scm_msa_unlock);
 101 +
 102  static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 103  {
 104         struct qcom_scm_desc desc = {
 105 --- a/drivers/firmware/qcom_scm.h
 106 +++ b/drivers/firmware/qcom_scm.h
 107 @@ -98,6 +98,8 @@ extern int scm_legacy_call(struct device
 108  #define QCOM_SCM_PIL_PAS_SHUTDOWN      0x06
 109  #define QCOM_SCM_PIL_PAS_IS_SUPPORTED  0x07
 110  #define QCOM_SCM_PIL_PAS_MSS_RESET     0x0a
 111 +#define QCOM_SCM_MSA_LOCK              0x24
 112 +#define QCOM_SCM_MSA_UNLOCK            0x25
 113
 114  #define QCOM_SCM_SVC_IO                        0x05
 115  #define QCOM_SCM_IO_READ               0x01
 116 --- a/include/linux/firmware/qcom/qcom_scm.h
 117 +++ b/include/linux/firmware/qcom/qcom_scm.h
 118 @@ -81,6 +81,8 @@ extern int qcom_scm_pas_mem_setup(u32 pe
 119  extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
 120  extern int qcom_scm_pas_shutdown(u32 peripheral);
 121  extern bool qcom_scm_pas_supported(u32 peripheral);
 122 +extern int qcom_scm_msa_lock(u32 peripheral);
 123 +extern int qcom_scm_msa_unlock(u32 peripheral);
 124
 125  extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
 126  extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);