git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From d1f1570f3d6db5d35642092a671812e62bfba79d Mon Sep 17 00:00:00 2001
   2 From: Varadarajan Narayanan <quic_varada@quicinc.com>
   3 Date: Tue, 30 Apr 2024 12:12:10 +0530
   4 Subject: [PATCH] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
   5
   6 Add interconnect-cells to clock provider so that it can be
   7 used as icc provider.
   8
   9 Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
  10 interfaces. This will be used by the gcc-ipq9574 driver
  11 that will for providing interconnect services using the
  12 icc-clk framework.
  13
  14 Acked-by: Georgi Djakov <djakov@kernel.org>
  15 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  16 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
  17 Link: https://lore.kernel.org/r/20240430064214.2030013-3-quic_varada@quicinc.com
  18 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  19 ---
  20  .../bindings/clock/qcom,ipq9574-gcc.yaml      |  3 +
  21  .../dt-bindings/interconnect/qcom,ipq9574.h   | 59 +++++++++++++++++++
  22  2 files changed, 62 insertions(+)
  23  create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
  24
  25 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
  26 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
  27 @@ -33,6 +33,9 @@ properties:
  28        - description: PCIE30 PHY3 pipe clock source
  29        - description: USB3 PHY pipe clock source
  30
  31 +  '#interconnect-cells':
  32 +    const: 1
  33 +
  34  required:
  35    - compatible
  36    - clocks
  37 --- /dev/null
  38 +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
  39 @@ -0,0 +1,59 @@
  40 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  41 +#ifndef INTERCONNECT_QCOM_IPQ9574_H
  42 +#define INTERCONNECT_QCOM_IPQ9574_H
  43 +
  44 +#define MASTER_ANOC_PCIE0              0
  45 +#define SLAVE_ANOC_PCIE0               1
  46 +#define MASTER_SNOC_PCIE0              2
  47 +#define SLAVE_SNOC_PCIE0               3
  48 +#define MASTER_ANOC_PCIE1              4
  49 +#define SLAVE_ANOC_PCIE1               5
  50 +#define MASTER_SNOC_PCIE1              6
  51 +#define SLAVE_SNOC_PCIE1               7
  52 +#define MASTER_ANOC_PCIE2              8
  53 +#define SLAVE_ANOC_PCIE2               9
  54 +#define MASTER_SNOC_PCIE2              10
  55 +#define SLAVE_SNOC_PCIE2               11
  56 +#define MASTER_ANOC_PCIE3              12
  57 +#define SLAVE_ANOC_PCIE3               13
  58 +#define MASTER_SNOC_PCIE3              14
  59 +#define SLAVE_SNOC_PCIE3               15
  60 +#define MASTER_USB                     16
  61 +#define SLAVE_USB                      17
  62 +#define MASTER_USB_AXI                 18
  63 +#define SLAVE_USB_AXI                  19
  64 +#define MASTER_NSSNOC_NSSCC            20
  65 +#define SLAVE_NSSNOC_NSSCC             21
  66 +#define MASTER_NSSNOC_SNOC_0           22
  67 +#define SLAVE_NSSNOC_SNOC_0            23
  68 +#define MASTER_NSSNOC_SNOC_1           24
  69 +#define SLAVE_NSSNOC_SNOC_1            25
  70 +#define MASTER_NSSNOC_PCNOC_1          26
  71 +#define SLAVE_NSSNOC_PCNOC_1           27
  72 +#define MASTER_NSSNOC_QOSGEN_REF       28
  73 +#define SLAVE_NSSNOC_QOSGEN_REF                29
  74 +#define MASTER_NSSNOC_TIMEOUT_REF      30
  75 +#define SLAVE_NSSNOC_TIMEOUT_REF       31
  76 +#define MASTER_NSSNOC_XO_DCD           32
  77 +#define SLAVE_NSSNOC_XO_DCD            33
  78 +#define MASTER_NSSNOC_ATB              34
  79 +#define SLAVE_NSSNOC_ATB               35
  80 +#define MASTER_MEM_NOC_NSSNOC          36
  81 +#define SLAVE_MEM_NOC_NSSNOC           37
  82 +#define MASTER_NSSNOC_MEMNOC           38
  83 +#define SLAVE_NSSNOC_MEMNOC            39
  84 +#define MASTER_NSSNOC_MEM_NOC_1                40
  85 +#define SLAVE_NSSNOC_MEM_NOC_1         41
  86 +
  87 +#define MASTER_NSSNOC_PPE              0
  88 +#define SLAVE_NSSNOC_PPE               1
  89 +#define MASTER_NSSNOC_PPE_CFG          2
  90 +#define SLAVE_NSSNOC_PPE_CFG           3
  91 +#define MASTER_NSSNOC_NSS_CSR          4
  92 +#define SLAVE_NSSNOC_NSS_CSR           5
  93 +#define MASTER_NSSNOC_IMEM_QSB         6
  94 +#define SLAVE_NSSNOC_IMEM_QSB          7
  95 +#define MASTER_NSSNOC_IMEM_AHB         8
  96 +#define SLAVE_NSSNOC_IMEM_AHB          9
  97 +
  98 +#endif /* INTERCONNECT_QCOM_IPQ9574_H */