git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
   2 From: Ziyang Huang <hzyitc@outlook.com>
   3 Date: Sun, 8 Sep 2024 16:40:12 +0800
   4 Subject: [PATCH] clk: gcc-ipq5018: refer to GE PHY rx and tx clk providers by name
   5
   6 QCA-SSDK does not register the output clocks of the onboard GE Phy and
   7 uniphy so the GCC and DTS can't reference them by their index.
   8 The SSDK references them by name, so let's change the GCC driver
   9 accordingly.
  10
  11 Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
  12 Signed-off-by: George Moussalem <george.moussalem@outlook.com>
  13 ---
  14  drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
  15  1 file changed, 8 insertions(+), 8 deletions(-)
  16
  17 --- a/drivers/clk/qcom/gcc-ipq5018.c
  18 +++ b/drivers/clk/qcom/gcc-ipq5018.c
  19 @@ -336,8 +336,8 @@ static const struct parent_map gcc_xo_gp
  20
  21  static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
  22         { .index = DT_XO },
  23 -       { .index = DT_GEPHY_RX_CLK },
  24 -       { .index = DT_GEPHY_TX_CLK },
  25 +       { .name =  "gephy_gcc_rx", .index = -1 },
  26 +       { .name =  "gephy_gcc_tx", .index = -1 },
  27         { .hw = &ubi32_pll.clkr.hw },
  28         { .hw = &gpll0.clkr.hw },
  29  };
  30 @@ -352,8 +352,8 @@ static const struct parent_map gcc_xo_ge
  31
  32  static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
  33         { .index = DT_XO },
  34 -       { .index = DT_GEPHY_TX_CLK },
  35 -       { .index = DT_GEPHY_RX_CLK },
  36 +       { .name =  "gephy_gcc_tx", .index = -1 },
  37 +       { .name =  "gephy_gcc_rx", .index = -1 },
  38         { .hw = &ubi32_pll.clkr.hw },
  39         { .hw = &gpll0.clkr.hw },
  40  };
  41 @@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
  42
  43  static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
  44         { .index = DT_XO },
  45 -       { .index = DT_UNIPHY_RX_CLK },
  46 -       { .index = DT_UNIPHY_TX_CLK },
  47 +       { .name =  "uniphy_gcc_rx", .index = -1 },
  48 +       { .name =  "uniphy_gcc_tx", .index = -1 },
  49         { .hw = &ubi32_pll.clkr.hw },
  50         { .hw = &gpll0.clkr.hw },
  51  };
  52 @@ -384,8 +384,8 @@ static const struct parent_map gcc_xo_un
  53
  54  static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
  55         { .index = DT_XO },
  56 -       { .index = DT_UNIPHY_TX_CLK },
  57 -       { .index = DT_UNIPHY_RX_CLK },
  58 +       { .name =  "uniphy_gcc_tx", .index = -1 },
  59 +       { .name =  "uniphy_gcc_rx", .index = -1 },
  60         { .hw = &ubi32_pll.clkr.hw },
  61         { .hw = &gpll0.clkr.hw },
  62  };