git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 777b8afb8179155353ec14b1d8153122410aba29 Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Sat, 15 Jun 2024 20:00:27 +0800
   4 Subject: [PATCH] net: phy: introduce core support for phy-mode = "10g-qxgmii"
   5
   6 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
   7 specification. It uses the same signaling as USXGMII, but it multiplexes
   8 4 ports over the link, resulting in a maximum speed of 2.5G per port.
   9
  10 Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
  11 either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
  12 they could get away just fine with that thus far. But there is a need to
  13 distinguish between the 2 as far as SerDes drivers are concerned.
  14
  15 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  16 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  17 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  18 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  19 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  20 ---
  21  Documentation/networking/phy.rst | 6 ++++++
  22  drivers/net/phy/phy-core.c       | 1 +
  23  drivers/net/phy/phylink.c        | 9 ++++++++-
  24  include/linux/phy.h              | 4 ++++
  25  include/linux/phylink.h          | 1 +
  26  5 files changed, 20 insertions(+), 1 deletion(-)
  27
  28 --- a/Documentation/networking/phy.rst
  29 +++ b/Documentation/networking/phy.rst
  30 @@ -327,6 +327,12 @@ Some of the interface modes are describe
  31      This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
  32      SGMII lines into a single link compared to 4 on QSGMII.
  33
  34 +``PHY_INTERFACE_MODE_10G_QXGMII``
  35 +    Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
  36 +    Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz
  37 +    SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
  38 +    through symbol replication. The PCS expects the standard USXGMII code word.
  39 +
  40  Pause frames / flow control
  41  ===========================
  42
  43 --- a/drivers/net/phy/phy-core.c
  44 +++ b/drivers/net/phy/phy-core.c
  45 @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interfac
  46                 return 1;
  47         case PHY_INTERFACE_MODE_QSGMII:
  48         case PHY_INTERFACE_MODE_QUSGMII:
  49 +       case PHY_INTERFACE_MODE_10G_QXGMII:
  50                 return 4;
  51         case PHY_INTERFACE_MODE_PSGMII:
  52                 return 5;
  53 --- a/drivers/net/phy/phylink.c
  54 +++ b/drivers/net/phy/phylink.c
  55 @@ -231,6 +231,7 @@ static int phylink_interface_max_speed(p
  56                 return SPEED_1000;
  57
  58         case PHY_INTERFACE_MODE_2500BASEX:
  59 +       case PHY_INTERFACE_MODE_10G_QXGMII:
  60                 return SPEED_2500;
  61
  62         case PHY_INTERFACE_MODE_5GBASER:
  63 @@ -500,7 +501,11 @@ unsigned long phylink_get_capabilities(p
  64
  65         switch (interface) {
  66         case PHY_INTERFACE_MODE_USXGMII:
  67 -               caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
  68 +               caps |= MAC_10000FD | MAC_5000FD;
  69 +               fallthrough;
  70 +
  71 +       case PHY_INTERFACE_MODE_10G_QXGMII:
  72 +               caps |= MAC_2500FD;
  73                 fallthrough;
  74
  75         case PHY_INTERFACE_MODE_RGMII_TXID:
  76 @@ -956,6 +961,7 @@ static int phylink_parse_mode(struct phy
  77                         phylink_set(pl->supported, 25000baseSR_Full);
  78                         fallthrough;
  79                 case PHY_INTERFACE_MODE_USXGMII:
  80 +               case PHY_INTERFACE_MODE_10G_QXGMII:
  81                 case PHY_INTERFACE_MODE_10GKR:
  82                 case PHY_INTERFACE_MODE_10GBASER:
  83                         phylink_set(pl->supported, 10baseT_Half);
  84 --- a/include/linux/phy.h
  85 +++ b/include/linux/phy.h
  86 @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_arr
  87   * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
  88   * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
  89   * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
  90 + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
  91   * @PHY_INTERFACE_MODE_MAX: Book keeping
  92   *
  93   * Describes the interface between the MAC and PHY.
  94 @@ -165,6 +166,7 @@ typedef enum {
  95         PHY_INTERFACE_MODE_10GKR,
  96         PHY_INTERFACE_MODE_QUSGMII,
  97         PHY_INTERFACE_MODE_1000BASEKX,
  98 +       PHY_INTERFACE_MODE_10G_QXGMII,
  99         PHY_INTERFACE_MODE_MAX,
 100  } phy_interface_t;
 101
 102 @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_
 103                 return "100base-x";
 104         case PHY_INTERFACE_MODE_QUSGMII:
 105                 return "qusgmii";
 106 +       case PHY_INTERFACE_MODE_10G_QXGMII:
 107 +               return "10g-qxgmii";
 108         default:
 109                 return "unknown";
 110         }
 111 --- a/include/linux/phylink.h
 112 +++ b/include/linux/phylink.h
 113 @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_n
 114         case PHY_INTERFACE_MODE_QSGMII:
 115         case PHY_INTERFACE_MODE_QUSGMII:
 116         case PHY_INTERFACE_MODE_USXGMII:
 117 +       case PHY_INTERFACE_MODE_10G_QXGMII:
 118                 /* These protocols are designed for use with a PHY which
 119                  * communicates its negotiation result back to the MAC via
 120                  * inband communication. Note: there exist PHYs that run
 121 @@ -714,6 +715,7 @@ static inline int phylink_get_link_timer
 122         case PHY_INTERFACE_MODE_SGMII:
 123         case PHY_INTERFACE_MODE_QSGMII:
 124         case PHY_INTERFACE_MODE_USXGMII:
 125 +       case PHY_INTERFACE_MODE_10G_QXGMII:
 126                 return 1600000;
 127
 128         case PHY_INTERFACE_MODE_1000BASEX: