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1 From e5104bc345222b6032af61c79f140f663e07207e Mon Sep 17 00:00:00 2001
2 From: Lee Jackson <lee.jackson@arducam.com>
3 Date: Wed, 10 Jan 2024 09:06:16 +0800
4 Subject: [PATCH 0823/1085] drivers: media: arducam_64mp: Add
5 V4L2_CID_LINK_FREQ control
6
7 Add V4L2_CID_LINK_FREQ as a read-only control with a value of 456 Mhz.
8 This will be used by the CFE driver to corretly setup the DPHY timing
9 parameters in the CSI-2 block.
10
11 Signed-off-by: Lee Jackson <lee.jackson@arducam.com>
12 ---
13 drivers/media/i2c/arducam_64mp.c | 16 ++++++++++++++++
14 1 file changed, 16 insertions(+)
15
16 --- a/drivers/media/i2c/arducam_64mp.c
17 +++ b/drivers/media/i2c/arducam_64mp.c
18 @@ -143,6 +143,10 @@ struct arducam_64mp_mode {
19 struct arducam_64mp_reg_list reg_list;
20 };
21
22 +static const s64 arducam_64mp_link_freq_menu[] = {
23 + ARDUCAM_64MP_DEFAULT_LINK_FREQ,
24 +};
25 +
26 static const struct arducam_64mp_reg mode_common_regs[] = {
27 {0x0100, 0x00},
28 {0x0136, 0x18},
29 @@ -2272,9 +2276,11 @@ static int arducam_64mp_init_controls(st
30 struct v4l2_ctrl_handler *ctrl_hdlr;
31 struct i2c_client *client = v4l2_get_subdevdata(&arducam_64mp->sd);
32 struct v4l2_fwnode_device_properties props;
33 + struct v4l2_ctrl *link_freq;
34 unsigned int i;
35 int ret;
36 u8 test_pattern_max;
37 + u8 link_freq_max;
38
39 ctrl_hdlr = &arducam_64mp->ctrl_handler;
40 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);
41 @@ -2292,6 +2298,16 @@ static int arducam_64mp_init_controls(st
42 ARDUCAM_64MP_PIXEL_RATE, 1,
43 ARDUCAM_64MP_PIXEL_RATE);
44
45 + /* LINK_FREQ is also read only */
46 + link_freq_max = ARRAY_SIZE(arducam_64mp_link_freq_menu) - 1;
47 + link_freq =
48 + v4l2_ctrl_new_int_menu(ctrl_hdlr, &arducam_64mp_ctrl_ops,
49 + V4L2_CID_LINK_FREQ,
50 + link_freq_max, 0,
51 + arducam_64mp_link_freq_menu);
52 + if (link_freq)
53 + link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
54 +
55 /*
56 * Create the controls here, but mode specific limits are setup
57 * in the arducam_64mp_set_framing_limits() call below.