git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 667885a6865832eb0678c7e02e47a3392f177ecb Mon Sep 17 00:00:00 2001
   2 From: Alexey Charkov <alchark@gmail.com>
   3 Date: Mon, 17 Jun 2024 22:28:57 +0400
   4 Subject: [PATCH] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588j
   5
   6 RK3588j is the 'industrial' variant of RK3588, and it uses a different
   7 set of OPPs both in terms of allowed frequencies and in terms of
   8 applicable voltages at each frequency setpoint.
   9
  10 Add the OPPs that apply to RK3588j (and apparently RK3588m too) to
  11 enable dynamic CPU frequency scaling.
  12
  13 OPP values are derived from Rockchip downstream sources [1] by taking
  14 only those OPPs which have the highest frequency for a given voltage
  15 level and dropping the rest (if they are included, the kernel complains
  16 at boot time about them being inefficient)
  17
  18 [1] https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  19
  20 Signed-off-by: Alexey Charkov <alchark@gmail.com>
  21 Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-7-c1f5f3267f1e@gmail.com
  22 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  23 ---
  24  arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 108 ++++++++++++++++++++++
  25  1 file changed, 108 insertions(+)
  26
  27 --- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
  28 +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
  29 @@ -5,3 +5,111 @@
  30   */
  31
  32  #include "rk3588-extra.dtsi"
  33 +
  34 +/ {
  35 +       cluster0_opp_table: opp-table-cluster0 {
  36 +               compatible = "operating-points-v2";
  37 +               opp-shared;
  38 +
  39 +               opp-1416000000 {
  40 +                       opp-hz = /bits/ 64 <1416000000>;
  41 +                       opp-microvolt = <750000 750000 950000>;
  42 +                       clock-latency-ns = <40000>;
  43 +                       opp-suspend;
  44 +               };
  45 +               opp-1608000000 {
  46 +                       opp-hz = /bits/ 64 <1608000000>;
  47 +                       opp-microvolt = <887500 887500 950000>;
  48 +                       clock-latency-ns = <40000>;
  49 +               };
  50 +               opp-1704000000 {
  51 +                       opp-hz = /bits/ 64 <1704000000>;
  52 +                       opp-microvolt = <937500 937500 950000>;
  53 +                       clock-latency-ns = <40000>;
  54 +               };
  55 +       };
  56 +
  57 +       cluster1_opp_table: opp-table-cluster1 {
  58 +               compatible = "operating-points-v2";
  59 +               opp-shared;
  60 +
  61 +               opp-1416000000 {
  62 +                       opp-hz = /bits/ 64 <1416000000>;
  63 +                       opp-microvolt = <750000 750000 950000>;
  64 +                       clock-latency-ns = <40000>;
  65 +               };
  66 +               opp-1608000000 {
  67 +                       opp-hz = /bits/ 64 <1608000000>;
  68 +                       opp-microvolt = <787500 787500 950000>;
  69 +                       clock-latency-ns = <40000>;
  70 +               };
  71 +               opp-1800000000 {
  72 +                       opp-hz = /bits/ 64 <1800000000>;
  73 +                       opp-microvolt = <875000 875000 950000>;
  74 +                       clock-latency-ns = <40000>;
  75 +               };
  76 +               opp-2016000000 {
  77 +                       opp-hz = /bits/ 64 <2016000000>;
  78 +                       opp-microvolt = <950000 950000 950000>;
  79 +                       clock-latency-ns = <40000>;
  80 +               };
  81 +       };
  82 +
  83 +       cluster2_opp_table: opp-table-cluster2 {
  84 +               compatible = "operating-points-v2";
  85 +               opp-shared;
  86 +
  87 +               opp-1416000000 {
  88 +                       opp-hz = /bits/ 64 <1416000000>;
  89 +                       opp-microvolt = <750000 750000 950000>;
  90 +                       clock-latency-ns = <40000>;
  91 +               };
  92 +               opp-1608000000 {
  93 +                       opp-hz = /bits/ 64 <1608000000>;
  94 +                       opp-microvolt = <787500 787500 950000>;
  95 +                       clock-latency-ns = <40000>;
  96 +               };
  97 +               opp-1800000000 {
  98 +                       opp-hz = /bits/ 64 <1800000000>;
  99 +                       opp-microvolt = <875000 875000 950000>;
 100 +                       clock-latency-ns = <40000>;
 101 +               };
 102 +               opp-2016000000 {
 103 +                       opp-hz = /bits/ 64 <2016000000>;
 104 +                       opp-microvolt = <950000 950000 950000>;
 105 +                       clock-latency-ns = <40000>;
 106 +               };
 107 +       };
 108 +};
 109 +
 110 +&cpu_b0 {
 111 +       operating-points-v2 = <&cluster1_opp_table>;
 112 +};
 113 +
 114 +&cpu_b1 {
 115 +       operating-points-v2 = <&cluster1_opp_table>;
 116 +};
 117 +
 118 +&cpu_b2 {
 119 +       operating-points-v2 = <&cluster2_opp_table>;
 120 +};
 121 +
 122 +&cpu_b3 {
 123 +       operating-points-v2 = <&cluster2_opp_table>;
 124 +};
 125 +
 126 +&cpu_l0 {
 127 +       operating-points-v2 = <&cluster0_opp_table>;
 128 +};
 129 +
 130 +&cpu_l1 {
 131 +       operating-points-v2 = <&cluster0_opp_table>;
 132 +};
 133 +
 134 +&cpu_l2 {
 135 +       operating-points-v2 = <&cluster0_opp_table>;
 136 +};
 137 +
 138 +&cpu_l3 {
 139 +       operating-points-v2 = <&cluster0_opp_table>;
 140 +};