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1 From 6e7370079669b0d55c9464bb7c3fb8fb7368b912 Mon Sep 17 00:00:00 2001
2 From: Sky Huang <skylake.huang@mediatek.com>
3 Date: Thu, 13 Feb 2025 16:05:50 +0800
4 Subject: [PATCH 11/20] net: phy: mediatek: Add token ring access helper
5 functions in mtk-phy-lib
6
7 This patch adds TR(token ring) manipulations and adds correct
8 macro names for those magic numbers. TR is a way to access
9 proprietary registers on page 52b5. Use these helper functions
10 so we can see which fields we're going to modify/set/clear.
11
12 TR functions with __* prefix mean that the operations inside
13 aren't wrapped by page select/restore functions.
14
15 This patch doesn't really change registers' settings but just
16 enhances readability and maintainability.
17
18 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
19 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
20 Link: https://patch.msgid.link/20250213080553.921434-3-SkyLake.Huang@mediatek.com
21 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
22 ---
23 drivers/net/phy/mediatek/mtk-ge-soc.c | 231 +++++++++++++++++--------
24 drivers/net/phy/mediatek/mtk-ge.c | 11 +-
25 drivers/net/phy/mediatek/mtk-phy-lib.c | 63 +++++++
26 drivers/net/phy/mediatek/mtk.h | 5 +
27 4 files changed, 230 insertions(+), 80 deletions(-)
28
29 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
30 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
31 @@ -25,6 +25,90 @@
32
33 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
34
35 +/* Registers on Token Ring debug nodes */
36 +/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
37 +/* NormMseLoThresh */
38 +#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
39 +
40 +/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
41 +/* RemAckCntLimitCtrl */
42 +#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
43 +
44 +/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
45 +/* VcoSlicerThreshBitsHigh */
46 +#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
47 +
48 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
49 +/* DfeTailEnableVgaThresh1000 */
50 +#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
51 +
52 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
53 +/* MrvlTrFix100Kp */
54 +#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
55 +/* MrvlTrFix100Kf */
56 +#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
57 +/* MrvlTrFix1000Kp */
58 +#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
59 +/* MrvlTrFix1000Kf */
60 +#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
61 +
62 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
63 +/* VgaDecRate */
64 +#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
65 +
66 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
67 +/* SlvDSPreadyTime */
68 +#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
69 +/* MasDSPreadyTime */
70 +#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
71 +
72 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
73 +/* ResetSyncOffset */
74 +#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
75 +
76 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
77 +/* FfeUpdGainForceVal */
78 +#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
79 +/* FfeUpdGainForce */
80 +#define FFE_UPDATE_GAIN_FORCE BIT(6)
81 +
82 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
83 +/* SS: Steady-state, KP: Proportional Gain */
84 +/* SSTrKp100 */
85 +#define SS_TR_KP100_MASK GENMASK(21, 19)
86 +/* SSTrKf100 */
87 +#define SS_TR_KF100_MASK GENMASK(18, 16)
88 +/* SSTrKp1000Mas */
89 +#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
90 +/* SSTrKf1000Mas */
91 +#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
92 +/* SSTrKp1000Slv */
93 +#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
94 +/* SSTrKf1000Slv */
95 +#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
96 +
97 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
98 +/* RegEEE_st2TrKf1000 */
99 +#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
100 +
101 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
102 +/* RegEEE_slv_waketr_timer_tar */
103 +#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
104 +/* RegEEE_slv_remtx_timer_tar */
105 +#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
106 +
107 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
108 +/* RegEEE_slv_wake_int_timer_tar */
109 +#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
110 +
111 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
112 +/* RegEEE_trfreeze_timer2 */
113 +#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
114 +
115 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
116 +/* RegEEE100Stg1_tar */
117 +#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
118 +
119 #define ANALOG_INTERNAL_OPERATION_MAX_US 20
120 #define TXRESERVE_MIN 0
121 #define TXRESERVE_MAX 7
122 @@ -700,40 +784,41 @@ restore:
123 static void mt798x_phy_common_finetune(struct phy_device *phydev)
124 {
125 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
126 - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
127 - __phy_write(phydev, 0x11, 0xc71);
128 - __phy_write(phydev, 0x12, 0xc);
129 - __phy_write(phydev, 0x10, 0x8fae);
130 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
131 + SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
132 + FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
133 + FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
134
135 /* EnabRandUpdTrig = 1 */
136 __phy_write(phydev, 0x11, 0x2f00);
137 __phy_write(phydev, 0x12, 0xe);
138 __phy_write(phydev, 0x10, 0x8fb0);
139
140 - /* NormMseLoThresh = 85 */
141 - __phy_write(phydev, 0x11, 0x55a0);
142 - __phy_write(phydev, 0x12, 0x0);
143 - __phy_write(phydev, 0x10, 0x83aa);
144 -
145 - /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
146 - __phy_write(phydev, 0x11, 0x240);
147 - __phy_write(phydev, 0x12, 0x0);
148 - __phy_write(phydev, 0x10, 0x9680);
149 + __mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
150 + NORMAL_MSE_LO_THRESH_MASK,
151 + FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
152 +
153 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
154 + FFE_UPDATE_GAIN_FORCE_VAL_MASK,
155 + FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
156 + FFE_UPDATE_GAIN_FORCE);
157
158 /* TrFreeze = 0 (mt7988 default) */
159 __phy_write(phydev, 0x11, 0x0);
160 __phy_write(phydev, 0x12, 0x0);
161 __phy_write(phydev, 0x10, 0x9686);
162
163 - /* SSTrKp100 = 5 */
164 - /* SSTrKf100 = 6 */
165 - /* SSTrKp1000Mas = 5 */
166 - /* SSTrKf1000Mas = 6 */
167 - /* SSTrKp1000Slv = 5 */
168 - /* SSTrKf1000Slv = 6 */
169 - __phy_write(phydev, 0x11, 0xbaef);
170 - __phy_write(phydev, 0x12, 0x2e);
171 - __phy_write(phydev, 0x10, 0x968c);
172 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
173 + SS_TR_KP100_MASK | SS_TR_KF100_MASK |
174 + SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
175 + SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
176 + FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
177 + FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
178 + FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
179 + FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
180 + FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
181 + FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
182 +
183 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
184 }
185
186 @@ -756,27 +841,29 @@ static void mt7981_phy_finetune(struct p
187 }
188
189 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
190 - /* ResetSyncOffset = 6 */
191 - __phy_write(phydev, 0x11, 0x600);
192 - __phy_write(phydev, 0x12, 0x0);
193 - __phy_write(phydev, 0x10, 0x8fc0);
194 -
195 - /* VgaDecRate = 1 */
196 - __phy_write(phydev, 0x11, 0x4c2a);
197 - __phy_write(phydev, 0x12, 0x3e);
198 - __phy_write(phydev, 0x10, 0x8fa4);
199 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
200 + RESET_SYNC_OFFSET_MASK,
201 + FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
202 +
203 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
204 + VGA_DECIMATION_RATE_MASK,
205 + FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
206
207 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
208 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
209 */
210 - __phy_write(phydev, 0x11, 0xd10a);
211 - __phy_write(phydev, 0x12, 0x34);
212 - __phy_write(phydev, 0x10, 0x8f82);
213 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
214 + MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
215 + MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
216 + FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
217 + FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
218 + FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
219 + FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
220
221 /* VcoSlicerThreshBitsHigh */
222 - __phy_write(phydev, 0x11, 0x5555);
223 - __phy_write(phydev, 0x12, 0x55);
224 - __phy_write(phydev, 0x10, 0x8ec0);
225 + __mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
226 + VCO_SLICER_THRESH_HIGH_MASK,
227 + FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
228 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
229
230 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
231 @@ -828,25 +915,23 @@ static void mt7988_phy_finetune(struct p
232 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
233
234 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
235 - /* ResetSyncOffset = 5 */
236 - __phy_write(phydev, 0x11, 0x500);
237 - __phy_write(phydev, 0x12, 0x0);
238 - __phy_write(phydev, 0x10, 0x8fc0);
239 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
240 + RESET_SYNC_OFFSET_MASK,
241 + FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
242
243 /* VgaDecRate is 1 at default on mt7988 */
244
245 - /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
246 - * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
247 - */
248 - __phy_write(phydev, 0x11, 0xb90a);
249 - __phy_write(phydev, 0x12, 0x6f);
250 - __phy_write(phydev, 0x10, 0x8f82);
251 -
252 - /* RemAckCntLimitCtrl = 1 */
253 - __phy_write(phydev, 0x11, 0xfbba);
254 - __phy_write(phydev, 0x12, 0xc3);
255 - __phy_write(phydev, 0x10, 0x87f8);
256 -
257 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
258 + MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
259 + MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
260 + FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
261 + FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
262 + FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
263 + FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
264 +
265 + __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
266 + REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
267 + FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
268 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
269
270 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
271 @@ -927,40 +1012,36 @@ static void mt798x_phy_eee(struct phy_de
272 __phy_write(phydev, 0x12, 0x0);
273 __phy_write(phydev, 0x10, 0x9690);
274
275 - /* REG_EEE_st2TrKf1000 = 2 */
276 - __phy_write(phydev, 0x11, 0x114f);
277 - __phy_write(phydev, 0x12, 0x2);
278 - __phy_write(phydev, 0x10, 0x969a);
279 -
280 - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
281 - __phy_write(phydev, 0x11, 0x3028);
282 - __phy_write(phydev, 0x12, 0x0);
283 - __phy_write(phydev, 0x10, 0x969e);
284 -
285 - /* RegEEE_slv_wake_int_timer_tar = 8 */
286 - __phy_write(phydev, 0x11, 0x5010);
287 - __phy_write(phydev, 0x12, 0x0);
288 - __phy_write(phydev, 0x10, 0x96a0);
289 -
290 - /* RegEEE_trfreeze_timer2 = 586 */
291 - __phy_write(phydev, 0x11, 0x24a);
292 - __phy_write(phydev, 0x12, 0x0);
293 - __phy_write(phydev, 0x10, 0x96a8);
294 -
295 - /* RegEEE100Stg1_tar = 16 */
296 - __phy_write(phydev, 0x11, 0x3210);
297 - __phy_write(phydev, 0x12, 0x0);
298 - __phy_write(phydev, 0x10, 0x96b8);
299 + __mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
300 + EEE1000_STAGE2_TR_KF_MASK,
301 + FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
302 +
303 + __mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
304 + SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
305 + FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
306 + FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
307 +
308 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
309 + SLAVE_WAKEINT_TIMER_MASK,
310 + FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
311 +
312 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
313 + TR_FREEZE_TIMER2_MASK,
314 + FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
315 +
316 + __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
317 + EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
318 + FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
319 + 0x10));
320
321 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
322 __phy_write(phydev, 0x11, 0x1463);
323 __phy_write(phydev, 0x12, 0x0);
324 __phy_write(phydev, 0x10, 0x96ca);
325
326 - /* DfeTailEnableVgaThresh1000 = 27 */
327 - __phy_write(phydev, 0x11, 0x36);
328 - __phy_write(phydev, 0x12, 0x0);
329 - __phy_write(phydev, 0x10, 0x8f80);
330 + __mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
331 + DFE_TAIL_EANBLE_VGA_TRHESH_1000,
332 + FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
333 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
334
335 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
336 --- a/drivers/net/phy/mediatek/mtk-ge.c
337 +++ b/drivers/net/phy/mediatek/mtk-ge.c
338 @@ -18,6 +18,10 @@
339
340 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
341
342 +/* Registers on Token Ring debug nodes */
343 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
344 +#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
345 +
346 /* Registers on MDIO_MMD_VEND1 */
347 #define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
348 #define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
349 @@ -42,11 +46,8 @@ static void mtk_gephy_config_init(struct
350 0, MTK_PHY_ENABLE_DOWNSHIFT);
351
352 /* Increase SlvDPSready time */
353 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
354 - __phy_write(phydev, 0x10, 0xafae);
355 - __phy_write(phydev, 0x12, 0x2f);
356 - __phy_write(phydev, 0x10, 0x8fae);
357 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
358 + mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
359 + FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
360
361 /* Adjust 100_mse_threshold */
362 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
363 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c
364 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
365 @@ -6,6 +6,69 @@
366
367 #include "mtk.h"
368
369 +/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
370 + * mtk_tr* functions: wrapped by page switching operations
371 + * __mtk_tr* functions: no page switching operations
372 + */
373 +
374 +static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
375 + u8 node_addr, u8 data_addr)
376 +{
377 + u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
378 +
379 + if (read)
380 + tr_cmd |= BIT(13);
381 +
382 + tr_cmd |= (((ch_addr & 0x3) << 11) |
383 + ((node_addr & 0xf) << 7) |
384 + ((data_addr & 0x3f) << 1));
385 + dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
386 + __phy_write(phydev, 0x10, tr_cmd);
387 +}
388 +
389 +static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
390 + u8 data_addr, u16 *tr_high, u16 *tr_low)
391 +{
392 + __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
393 + *tr_low = __phy_read(phydev, 0x11);
394 + *tr_high = __phy_read(phydev, 0x12);
395 + dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
396 + *tr_high, *tr_low);
397 +}
398 +
399 +static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
400 + u8 data_addr, u32 tr_data)
401 +{
402 + __phy_write(phydev, 0x11, tr_data & 0xffff);
403 + __phy_write(phydev, 0x12, tr_data >> 16);
404 + dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
405 + tr_data >> 16, tr_data & 0xffff);
406 + __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
407 +}
408 +
409 +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
410 + u8 data_addr, u32 mask, u32 set)
411 +{
412 + u32 tr_data;
413 + u16 tr_high;
414 + u16 tr_low;
415 +
416 + __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
417 + tr_data = (tr_high << 16) | tr_low;
418 + tr_data = (tr_data & ~mask) | set;
419 + __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
420 +}
421 +EXPORT_SYMBOL_GPL(__mtk_tr_modify);
422 +
423 +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
424 + u8 data_addr, u32 mask, u32 set)
425 +{
426 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
427 + __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
428 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
429 +}
430 +EXPORT_SYMBOL_GPL(mtk_tr_modify);
431 +
432 int mtk_phy_read_page(struct phy_device *phydev)
433 {
434 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
435 --- a/drivers/net/phy/mediatek/mtk.h
436 +++ b/drivers/net/phy/mediatek/mtk.h
437 @@ -68,6 +68,11 @@ struct mtk_socphy_priv {
438 unsigned long led_state;
439 };
440
441 +void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
442 + u8 data_addr, u32 mask, u32 set);
443 +void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
444 + u8 data_addr, u32 mask, u32 set);
445 +
446 int mtk_phy_read_page(struct phy_device *phydev);
447 int mtk_phy_write_page(struct phy_device *phydev, int page);
448
Mirror of https://github.com/openwrt/openwrt.git