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1 From c7f75954212b5e64f6b1f2375215b02fd79758ce Mon Sep 17 00:00:00 2001
2 From: Martin Schiller <ms@dev.tdt.de>
3 Date: Tue, 11 Jun 2024 15:54:23 +0200
4 Subject: dt-bindings: net: dsa: lantiq,gswip: convert to YAML schema
5
6 Convert the lantiq,gswip bindings to YAML format.
7
8 Also add this new file to the MAINTAINERS file.
9
10 Furthermore, the CPU port has to specify a phy-mode and either a phy or
11 a fixed-link. Since GSWIP is connected using a SoC internal protocol
12 there's no PHY involved. Add phy-mode = "internal" and a fixed-link to
13 the example code to describe the communication between the PMAC
14 (Ethernet controller) and GSWIP switch.
15
16 Signed-off-by: Martin Schiller <ms@dev.tdt.de>
17 Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
18 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
19 Link: https://lore.kernel.org/r/20240611135434.3180973-2-ms@dev.tdt.de
20 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
21 ---
22 .../devicetree/bindings/net/dsa/lantiq,gswip.yaml | 202 +++++++++++++++++++++
23 .../devicetree/bindings/net/dsa/lantiq-gswip.txt | 146 ---------------
24 MAINTAINERS | 1 +
25 3 files changed, 203 insertions(+), 146 deletions(-)
26 create mode 100644 Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
27 delete mode 100644 Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
28
29 --- /dev/null
30 +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
31 @@ -0,0 +1,202 @@
32 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
33 +%YAML 1.2
34 +---
35 +$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
36 +$schema: http://devicetree.org/meta-schemas/core.yaml#
37 +
38 +title: Lantiq GSWIP Ethernet switches
39 +
40 +allOf:
41 + - $ref: dsa.yaml#/$defs/ethernet-ports
42 +
43 +maintainers:
44 + - Hauke Mehrtens <hauke@hauke-m.de>
45 +
46 +properties:
47 + compatible:
48 + enum:
49 + - lantiq,xrx200-gswip
50 + - lantiq,xrx300-gswip
51 + - lantiq,xrx330-gswip
52 +
53 + reg:
54 + minItems: 3
55 + maxItems: 3
56 +
57 + reg-names:
58 + items:
59 + - const: switch
60 + - const: mdio
61 + - const: mii
62 +
63 + mdio:
64 + $ref: /schemas/net/mdio.yaml#
65 + unevaluatedProperties: false
66 +
67 + properties:
68 + compatible:
69 + const: lantiq,xrx200-mdio
70 +
71 + required:
72 + - compatible
73 +
74 + gphy-fw:
75 + type: object
76 + properties:
77 + '#address-cells':
78 + const: 1
79 +
80 + '#size-cells':
81 + const: 0
82 +
83 + compatible:
84 + items:
85 + - enum:
86 + - lantiq,xrx200-gphy-fw
87 + - lantiq,xrx300-gphy-fw
88 + - lantiq,xrx330-gphy-fw
89 + - const: lantiq,gphy-fw
90 +
91 + lantiq,rcu:
92 + $ref: /schemas/types.yaml#/definitions/phandle
93 + description: phandle to the RCU syscon
94 +
95 + patternProperties:
96 + "^gphy@[0-9a-f]{1,2}$":
97 + type: object
98 +
99 + additionalProperties: false
100 +
101 + properties:
102 + reg:
103 + minimum: 0
104 + maximum: 255
105 + description:
106 + Offset of the GPHY firmware register in the RCU register range
107 +
108 + resets:
109 + items:
110 + - description: GPHY reset line
111 +
112 + reset-names:
113 + items:
114 + - const: gphy
115 +
116 + required:
117 + - reg
118 +
119 + required:
120 + - compatible
121 + - lantiq,rcu
122 +
123 + additionalProperties: false
124 +
125 +required:
126 + - compatible
127 + - reg
128 +
129 +unevaluatedProperties: false
130 +
131 +examples:
132 + - |
133 + switch@e108000 {
134 + compatible = "lantiq,xrx200-gswip";
135 + reg = <0xe108000 0x3100>, /* switch */
136 + <0xe10b100 0xd8>, /* mdio */
137 + <0xe10b1d8 0x130>; /* mii */
138 + dsa,member = <0 0>;
139 +
140 + ports {
141 + #address-cells = <1>;
142 + #size-cells = <0>;
143 +
144 + port@0 {
145 + reg = <0>;
146 + label = "lan3";
147 + phy-mode = "rgmii";
148 + phy-handle = <&phy0>;
149 + };
150 +
151 + port@1 {
152 + reg = <1>;
153 + label = "lan4";
154 + phy-mode = "rgmii";
155 + phy-handle = <&phy1>;
156 + };
157 +
158 + port@2 {
159 + reg = <2>;
160 + label = "lan2";
161 + phy-mode = "internal";
162 + phy-handle = <&phy11>;
163 + };
164 +
165 + port@4 {
166 + reg = <4>;
167 + label = "lan1";
168 + phy-mode = "internal";
169 + phy-handle = <&phy13>;
170 + };
171 +
172 + port@5 {
173 + reg = <5>;
174 + label = "wan";
175 + phy-mode = "rgmii";
176 + phy-handle = <&phy5>;
177 + };
178 +
179 + port@6 {
180 + reg = <0x6>;
181 + phy-mode = "internal";
182 + ethernet = <&eth0>;
183 +
184 + fixed-link {
185 + speed = <1000>;
186 + full-duplex;
187 + };
188 + };
189 + };
190 +
191 + mdio {
192 + #address-cells = <1>;
193 + #size-cells = <0>;
194 + compatible = "lantiq,xrx200-mdio";
195 +
196 + phy0: ethernet-phy@0 {
197 + reg = <0x0>;
198 + };
199 + phy1: ethernet-phy@1 {
200 + reg = <0x1>;
201 + };
202 + phy5: ethernet-phy@5 {
203 + reg = <0x5>;
204 + };
205 + phy11: ethernet-phy@11 {
206 + reg = <0x11>;
207 + };
208 + phy13: ethernet-phy@13 {
209 + reg = <0x13>;
210 + };
211 + };
212 +
213 + gphy-fw {
214 + #address-cells = <1>;
215 + #size-cells = <0>;
216 + compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
217 + lantiq,rcu = <&rcu0>;
218 +
219 + gphy@20 {
220 + reg = <0x20>;
221 +
222 + resets = <&reset0 31 30>;
223 + reset-names = "gphy";
224 + };
225 +
226 + gphy@68 {
227 + reg = <0x68>;
228 +
229 + resets = <&reset0 29 28>;
230 + reset-names = "gphy";
231 + };
232 + };
233 + };
234 --- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
235 +++ /dev/null
236 @@ -1,146 +0,0 @@
237 -Lantiq GSWIP Ethernet switches
238 -==================================
239 -
240 -Required properties for GSWIP core:
241 -
242 -- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
243 - xRX200 SoC
244 - "lantiq,xrx300-gswip" for the embedded GSWIP in the
245 - xRX300 SoC
246 - "lantiq,xrx330-gswip" for the embedded GSWIP in the
247 - xRX330 SoC
248 -- reg : memory range of the GSWIP core registers
249 - : memory range of the GSWIP MDIO registers
250 - : memory range of the GSWIP MII registers
251 -
252 -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
253 -additional required and optional properties.
254 -
255 -
256 -Required properties for MDIO bus:
257 -- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
258 - core of the xRX200 SoC and the PHYs connected to it.
259 -
260 -See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
261 -required and optional properties.
262 -
263 -
264 -Required properties for GPHY firmware loading:
265 -- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
266 - "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
267 - "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
268 - for the loading of the firmware into the embedded
269 - GPHY core of the SoC.
270 -- lantiq,rcu : reference to the rcu syscon
271 -
272 -The GPHY firmware loader has a list of GPHY entries, one for each
273 -embedded GPHY
274 -
275 -- reg : Offset of the GPHY firmware register in the RCU
276 - register range
277 -- resets : list of resets of the embedded GPHY
278 -- reset-names : list of names of the resets
279 -
280 -Example:
281 -
282 -Ethernet switch on the VRX200 SoC:
283 -
284 -switch@e108000 {
285 - #address-cells = <1>;
286 - #size-cells = <0>;
287 - compatible = "lantiq,xrx200-gswip";
288 - reg = < 0xe108000 0x3100 /* switch */
289 - 0xe10b100 0xd8 /* mdio */
290 - 0xe10b1d8 0x130 /* mii */
291 - >;
292 - dsa,member = <0 0>;
293 -
294 - ports {
295 - #address-cells = <1>;
296 - #size-cells = <0>;
297 -
298 - port@0 {
299 - reg = <0>;
300 - label = "lan3";
301 - phy-mode = "rgmii";
302 - phy-handle = <&phy0>;
303 - };
304 -
305 - port@1 {
306 - reg = <1>;
307 - label = "lan4";
308 - phy-mode = "rgmii";
309 - phy-handle = <&phy1>;
310 - };
311 -
312 - port@2 {
313 - reg = <2>;
314 - label = "lan2";
315 - phy-mode = "internal";
316 - phy-handle = <&phy11>;
317 - };
318 -
319 - port@4 {
320 - reg = <4>;
321 - label = "lan1";
322 - phy-mode = "internal";
323 - phy-handle = <&phy13>;
324 - };
325 -
326 - port@5 {
327 - reg = <5>;
328 - label = "wan";
329 - phy-mode = "rgmii";
330 - phy-handle = <&phy5>;
331 - };
332 -
333 - port@6 {
334 - reg = <0x6>;
335 - ethernet = <&eth0>;
336 - };
337 - };
338 -
339 - mdio {
340 - #address-cells = <1>;
341 - #size-cells = <0>;
342 - compatible = "lantiq,xrx200-mdio";
343 - reg = <0>;
344 -
345 - phy0: ethernet-phy@0 {
346 - reg = <0x0>;
347 - };
348 - phy1: ethernet-phy@1 {
349 - reg = <0x1>;
350 - };
351 - phy5: ethernet-phy@5 {
352 - reg = <0x5>;
353 - };
354 - phy11: ethernet-phy@11 {
355 - reg = <0x11>;
356 - };
357 - phy13: ethernet-phy@13 {
358 - reg = <0x13>;
359 - };
360 - };
361 -
362 - gphy-fw {
363 - compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
364 - lantiq,rcu = <&rcu0>;
365 - #address-cells = <1>;
366 - #size-cells = <0>;
367 -
368 - gphy@20 {
369 - reg = <0x20>;
370 -
371 - resets = <&reset0 31 30>;
372 - reset-names = "gphy";
373 - };
374 -
375 - gphy@68 {
376 - reg = <0x68>;
377 -
378 - resets = <&reset0 29 28>;
379 - reset-names = "gphy";
380 - };
381 - };
382 -};
383 --- a/MAINTAINERS
384 +++ b/MAINTAINERS
385 @@ -11863,6 +11863,7 @@ LANTIQ / INTEL Ethernet drivers
386 M: Hauke Mehrtens <hauke@hauke-m.de>
387 L: netdev@vger.kernel.org
388 S: Maintained
389 +F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
390 F: drivers/net/dsa/lantiq_gswip.c
391 F: drivers/net/dsa/lantiq_pce.h
392 F: drivers/net/ethernet/lantiq_xrx200.c
Mirror of https://github.com/openwrt/openwrt.git